SN74AUCH16374 [TI]
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS; 16位边沿触发D型触发器具有三态输出
| 型号： | SN74AUCH16374 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS |
| 文件： | 总12页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
DGG OR DGV PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
1CLK
1D1
1D2
GND
1D3
1D4
2
3
I
Supports Partial-Power-Down Mode
off
4
Operation
5
Sub 1-V Operable
6
7
V
V
Max t of 2.8 ns at 1.8 V
pd
CC
CC
8
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
Low Power Consumption, 20 µA Max I
±8-mA Output Drive at 1.8 V
CC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
V
V
CC
CC
– 1000-V Charged-Device Model (C101)
2Q5
2Q6
GND
2Q7
2Q8
2OE
2D5
2D6
GND
2D7
2D8
2CLK
description/ordering information
This 16-bit edge-triggered D-type flip-flop is
operational at 0.8-V to 2.7-V V , but is designed
CC
specifically for 1.65-V to 1.95-V V
operation.
CC
The SN74AUCH16374 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two
8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the
flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
PACKAGE
TSSOP – DGG
A
Tape and reel
Tape and reel
Tape and reel
SN74AUCH16374DGGR
SN74AUCH16374DGVR
SN74AUCH16374GQLR
AUCH16374
MJ374
–40°C to 85°C TVSOP – DGV
VFBGA – GQL
MJ374
†
Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Activebus-holdcircuitryholdsunusedorundriveninputsatavalidlogicstate. Useofpulluporpulldownresistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
NC
NC
NC
NC
1CLK
1D2
1D4
1D6
1D8
2D1
2D3
2D5
2D7
2CLK
A
B
C
D
E
F
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
GND
GND
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
V
CC
V
CC
GND
GND
G
H
J
GND
GND
G
H
J
V
CC
V
CC
GND
NC
GND
NC
K
K
NC – No internal connection
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
CLK
D
H
L
OE
L
L
↑
↑
H
L
L
H or L
X
X
X
Q
0
H
Z
logic diagram (positive logic)
1
24
25
2OE
1OE
48
2CLK
1CLK
C1
C1
2
13
2Q1
1Q1
47
36
1D
2D1
1D1
1D
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
Supply voltage
0.8
2.7
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
V
CC
V
High-level input voltage
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
= 0.8 V
0.65 × V
V
V
CC
1.7
0
0.35 × V
0.7
V
IL
Low-level input voltage
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
CC
V
V
Input voltage
0
0
0
3.6
V
V
V
I
Active state
3-state
V
CC
3.6
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
= 1.1 V
= 1.4 V
= 1.65 V
= 2.3 V
= 0.8 V
= 1.1 V
= 1.4 V
= 1.65 V
= 2.3 V
–0.7
–3
–5
–8
–9
0.7
3
I
High-level output current
Low-level output current
mA
mA
OH
OL
I
5
8
9
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
20
85
ns/V
T
A
–40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
V –0.1
CC
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –0.7 mA
= –3 mA
= –5 mA
= –8 mA
= –9 mA
= 100 µA
= 0.7 mA
= 3 mA
0.8 V to 2.7 V
0.8 V
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
0.55
1.1 V
0.8
V
OH
V
1.4 V
1
1.65 V
2.3 V
1.2
1.8
0.8 V to 2.7 V
0.8 V
0.2
0.25
1.1 V
0.3
0.4
V
OL
V
= 5 mA
1.4 V
= 8 mA
1.65 V
2.3 V
0.45
0.6
= 9 mA
I
I
All inputs
V = V
or GND
0 to 2.7 V
1.1 V
±5
µA
µA
I
I
CC
V = 0.35 V
I
10
15
V = 0.47 V
I
1.4 V
‡
BHL
V = 0.57 V
I
1.65 V
2.3 V
20
V = 0.7 V
I
40
V = 0.8 V
I
1.1 V
–5
V = 0.9 V
1.4 V
–15
–20
–40
75
I
§
I
I
I
µA
µA
µA
BHH
V = 1.07 V
I
1.65 V
2.3 V
V = 1.7 V
I
1.3 V
1.6 V
125
175
275
–75
¶
V = 0 to V
I
BHLO
CC
CC
1.95 V
2.7 V
1.3 V
1.6 V
–125
–175
–275
#
V = 0 to V
I
BHHO
1.95 V
2.7 V
I
I
I
V or V = 2.7 V
0
±10
±10
20
µA
µA
µA
pF
pF
off
I
O
V
O
= V or GND
CC
2.7 V
OZ
CC
V = V
or GND,
or GND
I = 0
O
0.8 V to 2.7 V
2.5 V
I
CC
CC
C
C
V = V
I
3
5
i
V
O
= V or GND
CC
2.5 V
o
†
‡
All typical values are at T = 25°C.
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
A
should be measured after lowering V to GND and
IN
IL
BHL
§
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
¶
#
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V = 1.2 V
CC
± 0.1 V
V = 1.5 V
CC
± 0.1 V
V = 1.8 V
CC
± 0.15 V
V = 2.5 V
CC
± 0.2 V
V
CC
= 0.8 V
UNIT
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
85
5.9
1.4
0.1
250
250
250
250
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
1.9
1.2
0.4
1.9
0.7
0.4
1.9
0.6
0.4
1.9
0.6
0.4
w
ns
su
h
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 1.2 V
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
CC
± 0.1 V
CC
± 0.1 V
CC
± 0.15 V
CC
± 0.2 V
V
CC
= 0.8 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN MAX
MIN MAX
MIN TYP MAX
MIN MAX
f
t
t
t
85
7.3
7
250
250
250
250
MHz
ns
max
CLK
OE
1
1.2
2
4.5
5.3
7.1
0.8
0.8
1
2.9
3.6
4.8
0.7
0.8
1.4
1.5
1.5
2.7
2.8
2.9
4.5
0.7
0.7
0.5
2.2
2.2
2.2
Q
Q
Q
pd
ns
en
OE
8.2
ns
dis
†
operating characteristics, T = 25°C
A
V
CC
= 0.8 V
V
CC
= 1.2 V
V
CC
= 1.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
TYP
TYP
1 f = 5 MHz
data
1 f = 10 MHz
Outputs
enabled,
1 output
switching
‡
C
Power
dissipation
capacitance
pd
clk
1 f
= 5 MHz
24
24
24.1
26.2
9.4
31.2
13.2
pF
(each
output)
out
OE = GND
= 0 pF
C
L
Outputs
disabled, 1 f = 10 MHz
1 clock
and 1
data
1 f
= 5 MHz
data
clk
f = not
Power
dissipation
capacitance
C
pd
out
switching
OE = V
7.5
7.5
8
pF
pF
(Z)
CC
C = 0 pF
L
switching
1 f
= 0 MHz
data
Outputs
disabled,
clock
1 f = 10 MHz
§
clk
= not
C
Power
dissipation
pd
f
out
switching
OE = V
13.8
13.8
14
14.7
17.5
(each
clock)
capacitance only
switching
CC
= 0 pF
C
L
†
‡
Total device C for multiple (n) outputs switching and (y) clocks inputs switching = {n * C (each output)} + {y * C (each clock)}.
pd pd pd
C
(each output) is the C for each data bit (input and output circuitry) as it operates at 5 MHz (Note: the clock is operating at 10 MHz in this
pd
test, but its I
pd
component has been subtracted out).
pd
CC
(each clock) is the C for the clock circuitry only as it operates at 10 MHz.
§
C
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
S1
TEST
/t
S1
R
L
From Output
Under Test
t
Open
PLH PHL
t
/t
2 × V
CC
GND
PLZ PZL
C
L
t
/t
R
PHZ PZH
L
(see Note A)
V
C
R
V
∆
L
L
CC
0.8 V
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
15 pF
15 pF
15 pF
30 pF
30 pF
LOAD CIRCUIT
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
0.1 V
0.15 V
0.15 V
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
Input
0 V
0 V
t
t
t
t
t
PHL
/2
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
V
V
V
OH
CC
V
/2
/2
V
V
/2
/2
V
CC
Output
CC
CC
V
V
+ V
∆
S1 at 2 × V
(see Note B)
OL
CC
OL
OL
t
t
t
PLH
/2
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
SN74AUCH16374DGGR
SN74AUCH16374DGVR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
TVSOP
DGV
48
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74AUCH16374GQLR
SN74AUCH16374ZQLR
ACTIVE
ACTIVE
VFBGA
VFBGA
GQL
ZQL
56
56
1000
1000
None
SNPB
Level-1-240C-UNLIM
Level-1-260C-UNLIM
Pb-Free
(RoHS)
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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