SN74AUP1G125DPWR [TI]
具有三态输出的单路 0.8V 至 3.6V 低功耗缓冲器 | DPW | 5 | -40 to 85;型号: | SN74AUP1G125DPWR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有三态输出的单路 0.8V 至 3.6V 低功耗缓冲器 | DPW | 5 | -40 to 85 驱动 逻辑集成电路 |
文件: | 总15页 (文件大小:299K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES595E–JULY 2004–REVISED JULY 2005
FEATURES
•
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
•
•
•
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
Low Static-Power Consumption
(ICC = 0.0 µA Max)
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
Low Dynamic-Power Consumption
(Cpd = 4 pF Typ at 3.3 V)
•
•
•
tpd = 4.6 ns Max at 3.3 V
Suitable for Point-to-Point Applications
•
•
Low Input Capacitance (Ci = 1.5 pF Typ)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Low Noise – Overshoot and Undershoot
<10% of VCC
•
ESD Performance Tested Per JESD 22
•
•
•
Input-Disable Feature Allows Floating Input
Conditions
– 2000-V Humna-Body Model
(A114-B, Class II)
Ioff Supports Partial-Power-Down Mode
Operation
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Input Hysteresis Allows Slow Input Transition
and Better Switching Noise Immunity at Input
•
ESD Protection Exceeds ±5000 V With
Human-Body Model
YEP OR YZP PACKAGE
(BOTTOM VIEW)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
3
4
Y
GND
A
1
2
3
5
OE
A
V
CC
OE
A
V
1
2
3
5
CC
1
2
3
5
4
OE
A
V
Y
CC
2
1
5
V
OE
CC
4
GND
Y
4
GND
Y
GND
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figures 1 and 2).
xxxx
Switching Characteristics
†
Static-Power Consumption
Dynamic-Power Consumption
(pF)
at 25 MHz
(µA)
3.5
3
100%
80%
100%
2.5
2
80%
Input
Output
1.5
1
60%
40%
60%
40%
3.3-V
3.3-V
†
†
Logic
Logic
0.5
0
20%
0%
20%
0%
−0.5
20
Time − ns
AUP
0
5
10
15
25
35 40 45
AUP
30
†
Single, dual, and triple gates
†
AUP1G08 data at C = 15 pF
L
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
xxx
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES595E–JULY 2004–REVISED JULY 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is high. This device has the input-disable feature, which allows floating input signals.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
SN74AUP1G125YEPR
Reel of 3000
_ _ _ HM _
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
SN74AUP1G125YZPR
–40°C to 85°C
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
SN74AUP1G125DBVR
SN74AUP1G125DBVT
SN74AUP1G125DCKR
SN74AUP1G125DCKT
SN74AUP1G125DRLR
SOT (SOT-23) – DBV
H25_
HM_
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
L
A
H
H
L
L
L
H
X(1)
Z
(1) Floating inputs allowed.
LOGIC DIAGRAM (POSITIVE LOGIC)
1
OE
A
2
4
Y
2
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES595E–JULY 2004–REVISED JULY 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage range in the high or low state(2)
4.6
4.6
4.6
V
V
VO
VO
IIK
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±20
±50
206
252
142
132
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
DBV package
DCK package
DRL package
YEP/YZP package
θJA
Package thermal impedance(3)
°C/W
°C
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
3
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES595E–JULY 2004–REVISED JULY 2005
Recommended Operating Conditions(1)
MIN
MAX
3.6
UNIT
VCC
Supply voltage
0.8
V
VCC = 0.8 V
VCC
3.6
3.6
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 0.8 V
0.65 × VCC
VIH
High-level input voltage
V
V
1.6
2
3.6
3.6
0
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Active state
0
0
0
0
0
0.35 × VCC
0.7
VIL
Low-level input voltage
Output voltage
0.9
VCC
3.6
VO
V
3-state
VCC = 0.8 V
–20
–1.1
–1.7
–1.9
–3.1
–4
µA
VCC = 1.1 V
VCC = 1.4 V
IOH
High-level output current
VCC = 1.65 V
VCC = 2.3 V
mA
µA
VCC = 3 V
VCC = 0.8 V
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
IOL
Low-level output current
VCC = 1.65 V
VCC = 2.3 V
1.9
mA
3.1
VCC = 3 V
4
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
VCC = 0.8 V to 3.6 V
200
85
ns/V
TA
–40
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow of Floating CMOS Inputs, literature number SCBA004.
4
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES595E–JULY 2004–REVISED JULY 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VCC
UNIT
MIN
VCC – 0.1
0.75 × VCC
1.11
TYP
MAX
MIN
VCC – 0.1
0.7 × VCC
1.03
MAX
0.8 V to 3.6 V
1.1 V
IOH = –1.1 mA
IOH = –1.7 mA
IOH = –1.9 mA
IOH = –2.3 mA
IOH = –3.1 mA
IOH = –2.7 mA
IOH = –4 mA
IOL = 20 µA
1.4 V
1.65 V
1.32
1.3
VOL
V
2.05
1.97
2.3 V
3 V
1.9
1.85
2.72
2.67
2.6
2.55
0.8 V to 3.6 V
1.1 V
0.1
0.3 × VCC
0.31
0.1
0.3 × VCC
0.37
IOL = 1.1 mA
IOL = 1.7 mA
IOL = 1.9 mA
IOL = 2.3 mA
IOL = 3.1 mA
IOL = 2.7 mA
IOL = 4 mA
1.4 V
1.65 V
0.31
0.35
VOL
V
0.31
0.33
2.3 V
0.44
0.45
0.31
0.33
3 V
0.44
0.45
A or OE
input
II
VI = GND to 3.6 V
0 V to 3.6 V
0.1
0.5
µA
Ioff
VI or VO = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V
VO = VCC or GND
0 V
0 V to 0.2 V
3.6 V
0.2
0.2
0.6
0.6
0.5
µA
µA
µA
∆Ioff
IOZ
VI = GND or (VCC to 3.6 V),
OE = GND, IO = 0
ICC
0.8 V to 3.6 V
3.3 V
0.5
0.9
µA
VI = VCC – 0.6 V(1)
IO = 0
,
A input
40
50
OE input
110
120
∆ICC
µA
VI = GND to 3.6 V,
OE = VCC
All inputs
0.8 V to 3.6 V
0
0
(2)
0 V
1.5
1.5
3
Ci
VI = VCC or GND
VO = VCC or GND
pF
pF
3.6 V
3.6 V
Co
(1) One input at VCC – 0.6 V, other input at VCC or GND
(2) To show ICC is very low when the input-disable feature is enabled
5
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES595E–JULY 2004–REVISED JULY 2005
Switching Characteristics
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA = –40°C
to 85°C
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC
UNIT
MIN
TYP
18.1
7.4
5.2
4.1
2.9
2.4
19.1
9.3
6.6
5.3
3.8
3.2
12.1
4.1
2.9
2.9
1.8
2.2
MAX
MIN
MAX
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
4.3
3.3
2.6
2
12.6
8.5
6.8
4.7
3.8
2.7
1
15.3
10.2
8.3
tpd
A
Y
Y
Y
ns
1.3
1.1
1
5.8
1.7
4.6
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
5.1
4.1
3.2
2.5
2.1
15.9
10.5
8.7
6
3.6
2.5
2.1
1.6
1.4
19.2
12.7
10.3
7.2
ten
OE
OE
ns
ns
4.9
5.9
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.4
1.8
1
6.9
4.5
4.3
2.7
3.2
2.2
1.7
1.5
1
7.7
5.1
4.7
3.3
4
tdis
1
1.2
1.1
6
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES595E–JULY 2004–REVISED JULY 2005
Switching Characteristics
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA = –40°C
to 85°C
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC
UNIT
MIN
TYP
20.5
8.4
5.9
4.7
3.4
2.8
21.8
10.2
7.3
5.8
4.3
3.7
13
MAX
13.7
9.3
MIN
MAX
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
4.6
3.5
3.9
2.3
2.1
3.6
2.4
1.3
1.6
1.4
16.6
11.1
9.1
7.5
tpd
A or B
Y
Y
Y
ns
5.3
4.3
6.4
5.2
16.8
11.2
9.2
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
0.8 V
4.9
3.9
3.4
2.5
2.1
4.4
3.3
2.7
2.1
1.9
20.2
13.5
11
ten
OE
ns
ns
6.4
5.4
7.8
6.4
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
3.8
2.2
2.4
1.3
1.9
6.6
4.7
4.4
3.1
3.4
11.7
7.9
6.4
4.9
5
1.2
1.3
2.2
1.2
1.9
14
9.3
7.5
5.4
5.6
tdis
OE
7
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES595E–JULY 2004–REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Duration)
From Output
Under Test
C
L
1 MΩ
(see Note A)
LOAD CIRCUIT
V
= 1.2 V
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
CC
CC
CC
CC
V
CC
= 0.8 V
± 0.1 V
5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF
/2 /2 /2
± 0.1 V
± 0.15 V
± 0.2 V
± 0.3 V
C
L
5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF
V
M
V
CC
V
CC
V
V /2
CC
V
/2
CC
V
/2
CC
CC
V
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
t
w
V
CC
V /2
CC
V /2
CC
Input
V
I
0 V
V
M
V
M
Input
VOLTAGE WAVEFORMS
PULSE DURATION
0 V
t
t
t
PHL
PLH
V
V
OH
V
CC
V
V
V
M
M
Output
Timing Input
Data Input
V /2
CC
OL
0 V
t
PHL
PLH
t
su
t
h
V
V
OH
V
CC
V
M
M
Output
V /2
CC
V
/2
CC
OL
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t /t = 3 ns.
O
r f
C. The outputs are measured one at a time, with one transition per measurement.
D. and t are the same as t
E. All parameters and waveforms are not applicable to all devices.
t
.
pd
PLH
PHL
Figure 3. Load Circuit and Voltage Waveforms
8
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES595E–JULY 2004–REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 × V
CC
S1
5 kΩ
From Output
Under Test
GND
TEST
S1
t
/t
2 × V
C
PLZ PZL
CC
L
5 kΩ
(see Note A)
t
/t
GND
PHZ PZH
LOAD CIRCUIT
V
= 1.2 V
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
CC
CC
CC
CC
V
CC
= 0.8 V
± 0.1 V
5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF
/2 /2 /2
± 0.1 V
± 0.15 V
5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF
/2 /2 /2
± 0.2 V
± 0.3 V
C
L
V
M
V
CC
V
CC
V
V
CC
V
V
CC
CC
CC
V
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
V
CC
Output
Control
V /2
CC
V /2
CC
0 V
t
t
PZL
PLZ
Output
V
V
CC
Waveform 1
V
/2
/2
CC
S1 at 2 × V
V
+ V
CC
∆
OL
OL
(see Note B)
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
− V
∆
V
CC
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t /t = 3 ns.
O
r f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
t
t
and t
and t
are the same as t
.
dis
.
PLZ
PHZ
are the same as t
PZL
PZH
en
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2005
PACKAGING INFORMATION
Orderable Device
74AUP1G125DBVRE4
74AUP1G125DBVTE4
74AUP1G125DCKRE4
74AUP1G125DCKTE4
74AUP1G125DRLRG4
SN74AUP1G125DBVR
SN74AUP1G125DBVT
SN74AUP1G125DCKR
SN74AUP1G125DCKT
SN74AUP1G125DRLR
SN74AUP1G125YZPR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
5
5
5
5
5
5
5
5
5
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SC70
DBV
DCK
DCK
DRL
DBV
DBV
DCK
DCK
DRL
YZP
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOP
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SC70
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOP
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
WCSP
3000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
5
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-2/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
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