SN74AUP1T50DCKR [TI]
低功耗、1.8V/2.5V/3.3V 输入、3.3V CMOS 输出、单路施密特触发缓冲门 | DCK | 5 | -40 to 85;
| 型号： | SN74AUP1T50DCKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低功耗、1.8V/2.5V/3.3V 输入、3.3V CMOS 输出、单路施密特触发缓冲门 | DCK | 5 | -40 to 85 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总16页 (文件大小：1148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AUP1T50
www.ti.com.cn
ZHCSAE2A –OCTOBER 2012–REVISED MARCH 2013
低功耗，1.8/2.5/3.3V 输入，3.3V CMOS 输出，单路
施密特触发器缓冲栅极
查询样品: SN74AUP1T50
1
特性
•
•
单电源电压转换器
•
•
更多栅极选项请见www.ti.com/littlelogic
静电放电 (ESD) 性能测试符合 JESD 22 标准
输出电平高达电源 VCCCMOS 电平
–
–
–
–
1.8V 至 3.3V（VCC=3.3V 时）
2.5V 至 3.3V（VCC=3.3V 时）
1.8V 至 2.5V（VCC=2.5V 时）
3.3V 至 2.5V（VCC=2.5V 时）
–
2000V 人体模型
（A114-B，II 类）
–
1000V 充电器件模型 (C101)
DCK 封装
（顶视图）
•
施密特触发器输入抑制输入噪声并提供更佳的输出
信号完整性
•
•
I关闭支持部分断电 (VCC=0)
1
2
3
5
4
VCC
NC
A
极低静态功耗：
0.1µA
•
•
•
极低动态功耗：
0.9µA
GND
Y
锁断性能超过 100mA（符合 JESD 78，II 类规范
的要求）
提供无铅封装：SC-70 (DCK)
2mm x 2.1mm x 0.65mm（高度 1.1mm）
说明/订购信息
SN74AUP1T50 执行布尔函数 Y=A，此函数指定用于逻辑电平转换应用，此类应用的输出以电源 VCC为基准。
AUP 技术是行业最低功耗逻辑技术，此技术设计用于扩展运行中的电池寿命。 所有接受 1.8V LVCMOS 信号的输
入电平，同时由一个单 3.3V 或 2.5V VCC电源供电运行。 该产品还可以保持出色的信号完整性（请见Figure 1
和Figure 2）。
2.3V 至 3.6V 的宽 VCC范围有可能实现开关输出电平连接至外部控制器或处理器。
施密特触发器输入（正负输入转换之间的 ΔVT=210mV）改进了开关转换期间的抗扰度，这对于模拟混合模式设计
十分有用。 施密特触发器输入抑制输入噪声、确保输出信号的完整性并可实现慢输入信号转换。
I关闭特性可实现省电条件 (VCC=0V) ，这在便携式和移动应用中十分重要。 当 VCC=0V 时，介于 0V 至 3.6V 范围内
的信号可被施加到器件的输入和输出上。 在这些条件下，不会对器件造成损坏。
SN74AUP1T50 被设计成具有优化的 4mA 电流驱动能力以减少由高驱动输出导致的线路反射、过冲和下冲。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
English Data Sheet: SCES844
SN74AUP1T50
ZHCSAE2A –OCTOBER 2012–REVISED MARCH 2013
www.ti.com.cn
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTION TABLE
INPUTS
OUTPUT
(Lower Level Input)
(VCC CMOS)
A
H
L
Y
H
L
Supply VCC = 2.3 V to 2.7 V (2.5 V)
INPUTS
VT+ max = VIH min
VT- min = VIL max
OUTPUT
CMOS
A
B
Y
VIH = 1.1 V
VIL = 0.35 V
VOH = 1.85 V
VOL = 0.45 V
Supply VCC = 3 V to 3.6 V (3.3 V)
INPUTS
VT+ max = VIH min
VT- min = VIL max
OUTPUT
CMOS
A
B
Y
VIH = 1.19 V
VIL = 0.5 V
VOH = 2.55 V
VOL = 0.45 V
LOGIC DIAGRAM (SCHMITT-TRIGGER BUFFER GATE)
2
4
A
Y
Switching Characteristics
Static-Power Consumption
Dynamic-Power Consumption
(pF)
†
at 25 MHz
(µA)
3.5
3
100%
80%
100%
2.5
80%
2
1.5
1
Input
Output
60%
40%
60%
40%
3.3-V
3.3-V
†
Logic
†
Logic
0.5
0
20%
0%
20%
0%
−0.5
AUP
AUP
10
15 20
Time − ns
AUP1G08 data at C = 15 pF
0
5
25
35 40 45
30
†
Single, dual, and triple gates
†
L
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
2
Copyright © 2012–2013, Texas Instruments Incorporated
SN74AUP1T50
www.ti.com.cn
ZHCSAE2A –OCTOBER 2012–REVISED MARCH 2013
3.3 V
3.3 V
V
V
= 1.19 V
= 0.5 V
V
V
= 1.19 V
= 0.5 V
IH
IH
IL
IL
1.8-V
3.3-V
2.5-V
3.3-V
System
System
System
System
2.5 V
2.5 V
V
V
= 1.10 V
= 0.35 V
V
V
= 1.10 V
= 0.35 V
IH
IH
IL
IL
1.8-V
2.5-V
3.3-V
2.5-V
System
System
System
System
Figure 3. Typical Design Examples
3.3 V
1.8-V
System
3.3-V
System
V
OH
min
V
T+
max = V min = 1.19 V
IH
V
OL
max
V
T−
min = V max = 0.5 V
IL
Input Switching Waveform
Output Switching Waveform
Figure 4. Switching Thresholds for 1.8-V to 3.3-V Translation
Copyright © 2012–2013, Texas Instruments Incorporated
3
SN74AUP1T50
ZHCSAE2A –OCTOBER 2012–REVISED MARCH 2013
www.ti.com.cn
MAX UNIT
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
VCC
VI
Supply voltage range
Input voltage range(2)
4.6
4.6
4.6
V
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage range in the high or low state(2)
Input clamp current
V
–0.5 VCC + 0.5
V
VI < 0
–50
–50
±20
±50
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
Package thermal impedance(3)
Storage temperature range
θJA
DCK package
259 °C/W
150 °C
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
2.3
MAX
3.6
UNIT
VCC
VI
Supply voltage
Input voltage
Output voltage
V
V
V
0
0
3.6
VCC
–3.1
–4
VO
VCC = 2.3 V
VCC = 3 V
VCC = 2.3 V
VCC = 3 V
IOH
High-level output current
mA
3.1
4
IOL
TA
Low-level output current
mA
°C
Operating free-air temperature
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
4
Copyright © 2012–2013, Texas Instruments Incorporated
SN74AUP1T50
www.ti.com.cn
ZHCSAE2A –OCTOBER 2012–REVISED MARCH 2013
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
TA = –40°C
TA = 25°C
to 85°C
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN TYP MAX
MIN MAX
VT+
2.3 V to 2.7 V
3 V to 3.6 V
0.6
0.75
0.35
1.1
1.16
0.6
0.6
0.75 1.19
0.35 0.6
1.1
Positive-going input
threshold voltage
V
VT–
2.3 V to 2.7 V
Negative-going
input threshold
voltage
V
V
3 V to 3.6 V
0.5
0.85
0.5 0.85
ΔVT
Hysteresis
2.3 V to 2.7 V
3 V to 3.6 V
0.23
0.25
0.6
0.1
0.15 0.56
VCC – 0.1
0.6
0.56
(VT+ – VT–
)
IOH = –20 μA
2.3 V to 3.6 V
VCC – 0.1
2.05
IOH = –2.3 mA
IOH = –3.1 mA
IOH = –2.7 mA
IOH = –4 mA
1.97
1.85
2.67
2.55
2.3 V
VOH
1.9
V
V
2.72
3 V
2.3 V to 3.6 V
2.3 V
2.6
IOL = 20 μA
0.1
0.31
0.44
0.31
0.44
0.1
0.1
0.33
0.45
0.33
0.45
0.5
IOL = 2.3 mA
VOL
IOL = 3.1 mA
IOL = 2.7 mA
3 V
IOL = 4 mA
II
All inputs
VI = 3.6 V or GND
VI or VO = 0 V to 3.6 V
VI or VO = 3.6 V
VI = 3.6 V or GND, IO = 0
0 V to 3.6 V
0 V
μA
μA
μA
μA
Ioff
ΔIoff
ICC
0.1
0.5
0 V to 0.2 V
2.3 V to 3.6 V
0.2
0.5
0.5
0.9
One input at 0.3 V or 1.1 V,
Other inputs at 0 or VCC, IO = 0
2.3 V to 2.7 V
3 V to 3.6 V
4
ΔICC
μA
One input at 0.45 V or 1.2 V,
Other inputs at 0 or VCC, IO = 0
12
Ci
VI = VCC or GND
VO = VCC or GND
3.3 V
3.3 V
1.5
3
pF
pF
Co
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 1.8 V ± 0.15 V (unless otherwise noted)
(see Figure 5)
TA = –40°C
to 85°C
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
CL
UNIT
MIN TYP MAX MIN
MAX
6.8
5 pF
10 pF
15 pF
30 pF
1.8
2.3
2.6
3.8
2.3
2.8
3.1
4.4
2.9
3.4
3.8
5.1
0.5
1
7.9
tpd
A
Y
ns
1
8.7
1.5
10.8
Copyright © 2012–2013, Texas Instruments Incorporated
5
SN74AUP1T50
ZHCSAE2A –OCTOBER 2012–REVISED MARCH 2013
www.ti.com.cn
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 2.5 V ± 0.2 V (unless otherwise noted)
(see Figure 5)
TA = –40°C
to 85°C
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
CL
UNIT
MIN
1.8
2.2
2.6
3.7
TYP
2.3
2.8
3.2
4.4
MAX
3.1
MIN MAX
5 pF
10 pF
15 pF
30 pF
0.5
1
6
7.1
7.9
10
3.5
tpd
A
Y
ns
5.2
1
5.2
1.5
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 3.3 V ± 0.3 V (unless otherwise noted)
(see Figure 5)
TA = –40°C
to 85°C
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
CL
UNIT
MIN
2
TYP
2.7
3.1
3.5
4.7
MAX
3.5
MIN MAX
5 pF
10 pF
15 pF
30 pF
0.5
1
5.5
6.5
7.4
9.5
2.4
2.8
4
3.9
tpd
A
Y
ns
4.3
1
5.5
1.5
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, VI = 1.8 V ± 0.15 V (unless otherwise noted)
(see Figure 5)
TA = –40°C
to 85°C
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
CL
UNIT
MIN
1.6
2
TYP
2
MAX
2.5
MIN MAX
5 pF
10 pF
15 pF
30 pF
0.5
1
8
8.5
9.1
9.8
2.4
2.8
3.9
2.9
tpd
A
Y
ns
2.3
3.4
3.3
1
4.4
1.5
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, VI = 2.5 V ± 0.2 V (unless otherwise noted)
(see Figure 5)
TA = –40°C
to 85°C
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
CL
UNIT
MIN
1.6
2
TYP
1.9
2.3
2.7
3.8
MAX
2.4
MIN MAX
5 pF
10 pF
15 pF
30 pF
0.5
1
5.3
6.1
6.8
8.5
2.7
tpd
A
Y
ns
2.3
3.4
3.1
1
4.2
1.5
6
Copyright © 2012–2013, Texas Instruments Incorporated
SN74AUP1T50
www.ti.com.cn
ZHCSAE2A –OCTOBER 2012–REVISED MARCH 2013
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, VI = 3.3 V ± 0.3 V (unless otherwise noted)
(see Figure 5)
TA = –40°C
to 85°C
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
CL
UNIT
MIN
1.6
2
TYP
2.1
2.4
2.7
3.8
MAX
2.7
3
MIN MAX
5 pF
10 pF
15 pF
30 pF
0.5
1
4.7
5.7
6.2
7.8
tpd
A
Y
ns
2.3
3.4
3.3
4.4
1
1.5
OPERATING CHARACTERISTICS
TA = 25°C
VCC = 2.5 V
VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
Cpd
Power dissipation capacitance
f = 10 MHz
4
5
pF
Copyright © 2012–2013, Texas Instruments Incorporated
7
SN74AUP1T50
ZHCSAE2A –OCTOBER 2012–REVISED MARCH 2013
www.ti.com.cn
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
V
CC
= 2.5 V
V
CC
= 3.3 V
± 0.2 V
5, 10, 15, 30 pF 5, 10, 15, 30 pF
V /2 V /2
± 0.3 V
C
L
1 MΩ
(see Note A)
C
L
V
MI
I
I
V
MO
V /2
CC
V /2
CC
LOAD CIRCUIT
V
I
V
MI
V
MI
Input
0 V
t
t
t
PHL
PLH
V
V
OH
V
V
V
Mo
MO
Output
OL
t
PHL
PLH
V
V
OH
V
Mo
Mo
Output
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
C. The outputs are measured one at a time, with one transition per measurement.
D.
t
and t are the same as t .
PHL pd
PLH
Figure 5. Load Circuit and Voltage Waveforms
8
Copyright © 2012–2013, Texas Instruments Incorporated
SN74AUP1T50
www.ti.com.cn
ZHCSAE2A –OCTOBER 2012–REVISED MARCH 2013
REVISION HISTORY
Changes from Original (October 2012) to Revision A
Page
•
更新文档以匹配 SN74AUP1T17 ........................................................................................................................................... 1
Copyright © 2012–2013, Texas Instruments Incorporated
9
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74AUP1T50DCKR
ACTIVE
SC70
DCK
5
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
U35
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AUP1T50DCKR
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2016
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SC70 DCK
SPQ
Length (mm) Width (mm) Height (mm)
180.0 180.0 18.0
SN74AUP1T50DCKR
5
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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