SN74AUP1T58YEPR [TI]
SPECIALTY INTERFACE CIRCUIT, BGA6, DIE SIZE, BGA-6;
| 型号： | SN74AUP1T58YEPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SPECIALTY INTERFACE CIRCUIT, BGA6, DIE SIZE, BGA-6 接口集成电路 |
| 文件： | 总15页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢀꢋ ꢁꢌ ꢍ ꢎꢏꢀꢅꢆ ꢆꢍꢐ ꢑꢒ ꢍꢈꢄꢌ ꢎ ꢍ ꢎꢑꢎ ꢍ ꢈ ꢓꢄꢁ ꢀꢍ ꢄꢈꢒ ꢓ
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SCES612B – OCTOBER 2004 − −REVISED DECEMBER 2004
D
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
Single-Supply Voltage Translator
D
D
D
D
Very Low Static and Dynamic Power
Consumption
Pb-Free Packages Available: SOT-23 (DBV),
SC−70 (DCK), WCSP (NanoFree)
− 1.8 V to 3.3 V (at V
− 2.5 V to 3.3 V (at V
− 1.8 V to 2.5 V (at V
− 3.3 V to 2.5 V (at V
= 3.3 V)
= 3.3 V)
= 2.5 V)
= 2.5 V)
CC
CC
CC
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
D
D
D
D
Nine Configurable Gate Logic Functions
Schmitt-Trigger Inputs Reject Input Noise
and Provide Better Output Signal Integrity
I
Supports Partial-Power-Down Mode
off
With Low Leakage Current (0.5 mA)
D
Related Devices: AUP1T98/97/57
200-ns/V Input Rise/Fall Time Allows Slow
Transition of Input Signal
DBV OR DCK PACKAGE
(TOP VIEW)
YEP OR YZP PACKAGE
(BOTTOM VIEW)
3 4
2 5
1 6
A
GND
B
Y
V
C
1
2
3
6
5
4
B
GND
A
C
V
Y
CC
CC
description/ordering information
AUP technology is the industry’s lowest-power logic technology designed for use in battery-operated or battery
backed−up equipment. The SN74AUP1T58 is designed for logic level translation applications with input
switching levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V V
supply.
CC
The wide V
range of 2.3 V to 3.6 V allows the possibility of battery voltage drop during system operation and
CC
ensures normal operation between this range.
Schmitt-trigger inputs ( nV = 210 mV between positive and negative input transitions) offer improved noise
T
immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger
inputs reject input noise, ensure integrity of output signals, and also allow for slow input signal transition.
The AUP1T58 can be easily configured to perform a required gate function by connecting A, B, and C inputs
to V
performed.
or ground (see Function Selection Table). Up to nine commonly used logic gate functions can be
CC
I
is a feature that allows for powered−down conditions (V
= 0 V) and is important in portable and mobile
CC
off
applications. When V
of the device. No damage will occur to the device under these conditions.
= 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs
CC
AUP1T58 is designed with optimized current drive capability of 4 mA to reduce line reflections, overshoot, and
undershoot caused by high drive outputs.
Nanostar and Nanofree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢔꢋ ꢈ ꢕ ꢁ ꢋ ꢁꢎ ꢖ ꢒꢁꢗ ꢋ ꢌꢅ ꢓꢄꢘ ꢍꢎ ꢌ ꢄꢈꢎ ꢍꢒ ꢌꢋ ꢖ ꢗ ꢅꢁꢖꢈ ꢋꢒ ꢁ ꢀ
SCES612B – OCTOBER 2004 − −REVISED DECEMBER 2004
description/ordering information (continued)
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Tape and reel SN74AUP1T58YEPR
Tape and reel SN74AUP1T58YZPR
_ _ _TJ_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
−40°C to 85°C
SOT (SOT-23) − DBV
Tape and reel SN74AUP1T58DBVR
Tape and reel SN74AUP1T58DCKR
HT5_
TJ_
SOT (SC-70) − DCK
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin
1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
FUNCTION SELECTION TABLE
LOGIC FUNCTION
2-input NAND gate
FIGURE NO.
5
5
2-input OR gate with both inputs inverted
2-input AND gate with inverted input
2-input NOR gate with inverted input
2-input NAND gate with both inputs inverted
2-input OR gate
6, 7
6, 7
8
8
2-input XOR gate
9
Inverter
10
11
Noninverted buffer
2
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ꢔ ꢋꢈ ꢕ ꢁꢋ ꢁꢎ ꢖꢒ ꢁꢗ ꢋꢌ ꢅꢓ ꢄꢘꢍ ꢎ ꢌ ꢄꢈ ꢎ ꢍ ꢒ ꢌꢋ ꢖ ꢗ ꢅꢁ ꢖ ꢈꢋ ꢒ ꢁꢀ
SCES612B – OCTOBER 2004 − −REVISED DECEMBER 2004
Switching Characteristics
Static-Power Consumption
Dynamic-Power Consumption
(pF)
†
at 25 MHz
(µA)
3.5
3
100%
80%
100%
2.5
2
80%
Input
Output
60%
40%
1.5
1
60%
40%
3.3-V
3.3-V
Logic
†
Logic
†
0.5
0
20%
0%
20%
0%
−0.5
AUP
AUP
10
15 20
Time − ns
0
5
25
35 40 45
30
†
Single, dual, and triple gates
†
AUP1G08 data at C = 15 pF
L
Figure 2. Excellent Signal Integrity
Figure 1. AUP − The Lowest-Power Family
3.3 V
3.3 V
V
IH
V
IL
= 1.19 V
= 0.5 V
V
IH
V
IL
= 1.19 V
= 0.5 V
1.8-V
3.3-V
2.5-V
3.3-V
System
System
System
System
AUP1T58
2.5 V
AUP1T58
2.5 V
V
IH
V
IL
= 1.10 V
= 0.35 V
V
IH
V
IL
= 1.10 V
= 0.35 V
1.8-V
2.5-V
3.3-V
2.5-V
System
System
System
System
AUP1T58
AUP1T58
Figure 3. Possible Voltage Translation Combinations
3.3 V
1.8-V
System
3.3-V
System
AUP1T58
V
min
max
OH
V +(max) = V (min) = 1.19 V
IH
T
V
V −(min) = V (max) = 0.5 V
OL
T
IL
Input Switching Waveform
Output Switching Waveform
Figure 4. Switching Thresholds for 1.8-V to 3.3-V Translation
3
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ꢔꢋ ꢈ ꢕ ꢁ ꢋ ꢁꢎ ꢖ ꢒꢁꢗ ꢋ ꢌꢅ ꢓꢄꢘ ꢍꢎ ꢌ ꢄꢈꢎ ꢍꢒ ꢌꢋ ꢖ ꢗ ꢅꢁꢖꢈ ꢋꢒ ꢁ ꢀ
SCES612B – OCTOBER 2004 − −REVISED DECEMBER 2004
FUNCTION TABLE
INPUTS
OUTPUT
Y
C
L
B
L
A
L
L
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
L
H
H
H
H
L
H
L
H
H
H
L
logic diagram (positive logic)
3
A
4
Y
1
B
6
C
4
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SCES612B – OCTOBER 2004 − −REVISED DECEMBER 2004
logic configurations
V
CC
V
CC
B
B
Y
Y
Y
C
C
B
B
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
C
Y
B
B
C
Y
C
Figure 5. 00/14+32: 2-Input NAND Gate
2-Input OR Gate
Figure 6. 14+08/14+02: 2-Input AND Gate
With Inverted B Input
2-Input NOR Gate With Inverted Input
With Both Inputs Inverted
V
CC
V
CC
A
A
C
Y
Y
C
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
C
Y
A
C
A
C
Y
Y
A
A
Figure 7. 14+08/14+02: 2-Input AND Gate
With Inverted C Input
2-Input NOR Gate With Inverted Input
Figure 8. 32/14+00: 2-Input OR Gate
2-Input NAND Gate
With Both Inputs Inverted
V
CC
V
CC
B
C
B
1
2
3
6
5
4
1
2
3
6
5
4
C
Y
A
Y
B
Y
Y
GND
Figure 9. 86: 2-Input XOR Gate
Figure 10. 04/14: Inverter
V
CC
1
6
5
4
A
Y
2
3
Y
A
GND
Figure 11. 17/34: Noninverted Buffer
5
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SCES612B – OCTOBER 2004 − −REVISED DECEMBER 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Output voltage range in the high or low state, V (see Note 1) . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous current through V
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
CC
Package thermal impedance, θ (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
2.3
MAX
3.6
UNIT
V
V
V
Supply voltage
Input voltage
Output voltage
V
V
V
CC
0
0
3.6
I
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 V
−3.1
−4
I
High-level output current
Low-level output current
mA
mA
OH
= 3 V
= 2.3 V
3.1
4
I
OL
= 3 V
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
= 2.3 V to 3.6 V
200
85
ns/V
T
−40
°C
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
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SCES612B – OCTOBER 2004 − −REVISED DECEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= −40°C
TO 85°C
A
T
A
= 25°C
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
MAX
V
T+
2.3 V to 2.7 V
3 V to 3.6 V
0.6
1.1
0.6
1.1
Positive-going
input threshold
voltage
V
0.75
0.35
0.5
1.16
0.6
0.75
0.35
0.5
1.19
0.6
V
T−
2.3 V to 2.7 V
Negative-going
input threshold
voltage
V
V
3 V to 3.6 V
0.85
0.85
∆V
Hysteresis
(V − V
T+
2.3 V to 2.7 V
0.23
0.25
0.6
0.17
0.21
0.6
T
3 V to 3.6 V
0.56
0.56
)
T−
I
I
I
I
I
I
I
I
I
I
= −20 µA
2.3 V to 3.6 V
V
− 0.1
V
CC
− 0.1
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
CC
2.05
= −2.3 mA
= −3.1 mA
= −2.7 mA
= −4 mA
= 20 µA
1.97
1.85
2.67
2.55
2.3 V
1.9
2.72
2.6
V
V
V
OH
3 V
2.3 V to 3.6 V
0.1
0.31
0.44
0.31
0.44
0.1
0.1
0.33
0.45
0.33
0.45
0.5
= 2.3 mA
= 3.1 mA
= 2.7 mA
= 4 mA
2.3 V
3 V
V
OL
I
I
All inputs
V = 3.6 V or GND
0 V to 3.6 V
0 V
µA
µA
µA
µA
I
I
V or V = 0 V to 3.6 V
0.1
0.5
off
I
O
∆I
V or V = 5.5 V
0 V to 0.2 V
2.3 V to 3.6 V
0.2
0.5
off
I
O
I
V = 3.6 V or GND, I = 0
0.5
0.9
CC
I
O
One input at 0.3 V or 1.1 V,
Other inputs at 0 or V , I = 0
2.3 V to 2.7 V
3 V to 3.6 V
4
CC
One input at 0.45 V or 1.2 V,
Other inputs at 0 or V , I = 0
O
∆I
CC
µA
12
CC
O
C
C
V = V
CC
or GND
or GND
3.3 V
3.3 V
1.5
3
pF
pF
i
I
V = V
O CC
o
switching characteristics over recommended operating free-air temperature range,
= 2.5 V + 0.2 V, V = 1.8 V + 0.15 V (unless otherwise noted) (see Figure 12)
V
CC
I
T
= −40°C
TO 85°C
A
T
A
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
C
UNIT
L
MIN
1.8
2.3
2.6
TYP
2.3
2.8
3.1
MAX
2.9
MIN
0.5
1
MAX
6.8
5 pF
10 pF
15 pF
30 pF
3.4
7.9
t
pd
A, B, or C
ns
Y
3.8
1
8.7
3.8
4.4
5.1
1.5
10.8
7
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈ ꢉꢊ
ꢀ ꢋꢁ ꢌꢍ ꢎꢏ ꢀꢅ ꢆꢆꢍꢐ ꢑ ꢒꢍꢈꢄꢌ ꢎ ꢍꢎ ꢑ ꢎ ꢍ ꢈꢓ ꢄꢁꢀ ꢍꢄꢈꢒ ꢓ
ꢔꢋ ꢈ ꢕ ꢁ ꢋ ꢁꢎ ꢖ ꢒꢁꢗ ꢋ ꢌꢅ ꢓꢄꢘ ꢍꢎ ꢌ ꢄꢈꢎ ꢍꢒ ꢌꢋ ꢖ ꢗ ꢅꢁꢖꢈ ꢋꢒ ꢁ ꢀ
SCES612B – OCTOBER 2004 − −REVISED DECEMBER 2004
switching characteristics over recommended operating free-air temperature range,
= 2.5 V + 0.2 V, V = 2.5 V + 0.2 V (unless otherwise noted) (see Figure 12)
V
CC
I
T
= −40°C
TO 85°C
A
T
A
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
C
UNIT
L
MIN
1.8
2.2
2.6
TYP
2.3
2.8
3.2
MAX
3.1
MIN
0.5
1
MAX
6
5 pF
10 pF
15 pF
30 pF
3.5
7.1
7.9
t
pd
A, B, or C
ns
Y
5.2
1
3.7
4.4
5.2
1.5
10
switching characteristics over recommended operating free-air temperature range,
= 2.5 V + 0.2 V, V = 3.3 V + 0.3 V (unless otherwise noted) (see Figure 12)
V
CC
I
T
= −40°C
TO 85°C
A
T
A
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
C
UNIT
L
MIN
2
TYP
2.7
3.1
3.5
MAX
3.5
MIN
0.5
1
MAX
5.5
5 pF
10 pF
15 pF
30 pF
2.4
2.8
3.9
6.5
t
pd
A, B, or C
ns
Y
4.3
1
7.4
4
4.7
5.5
1.5
9.5
switching characteristics over recommended operating free-air temperature range,
= 3.3 V + 0.3 V, V = 1.8 V + 0.15 V (unless otherwise noted) (see Figure 12)
V
CC
I
T
= −40°C
TO 85°C
A
T
A
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
C
UNIT
L
MIN
1.6
2
TYP
2
MAX
2.5
MIN
0.5
1
MAX
8
5 pF
10 pF
15 pF
30 pF
2.4
2.8
2.9
8.5
9.1
t
pd
A, B, or C
ns
Y
2.3
3.3
1
3.4
3.9
4.4
1.5
9.8
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V + 0.3 V, V = 2.5 V + 0.2 V (unless otherwise noted) (see Figure 12)
CC
I
T
= −40°C
TO 85°C
A
T
A
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
C
UNIT
L
MIN
1.6
2
TYP
1.9
2.3
2.7
MAX
2.4
MIN
0.5
1
MAX
5.3
5 pF
10 pF
15 pF
30 pF
2.7
6.1
t
pd
A, B, or C
ns
Y
2.3
3.1
1
6.8
3.4
3.8
4.2
1.5
8.5
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ
ꢀꢋ ꢁꢌ ꢍ ꢎꢏꢀꢅꢆ ꢆꢍꢐ ꢑꢒ ꢍꢈꢄꢌ ꢎ ꢍ ꢎꢑꢎ ꢍ ꢈ ꢓꢄꢁ ꢀꢍ ꢄꢈꢒ ꢓ
ꢔ ꢋꢈ ꢕ ꢁꢋ ꢁꢎ ꢖꢒ ꢁꢗ ꢋꢌ ꢅꢓ ꢄꢘꢍ ꢎ ꢌ ꢄꢈ ꢎ ꢍ ꢒ ꢌꢋ ꢖ ꢗ ꢅꢁ ꢖ ꢈꢋ ꢒ ꢁꢀ
SCES612B – OCTOBER 2004 − −REVISED DECEMBER 2004
switching characteristics over recommended operating free-air temperature range,
= 3.3 V + 0.3 V, V = 3.3 V + 0.3 V (unless otherwise noted) (see Figure 12)
V
CC
I
T
= −40°C
TO 85°C
A
T
A
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
C
UNIT
L
MIN
1.6
2
TYP
2.1
2.4
2.7
MAX
2.7
3
MIN
0.5
1
MAX
4.7
5 pF
10 pF
15 pF
30 pF
5.7
t
pd
A, B, or C
ns
Y
2.3
3.3
1
6.2
3.4
3.8
4.4
1.5
7.8
operating characteristics, T = 25°C
A
V
CC
= 2.5 V
V
CC
= 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
C
Power dissipation capacitance
f = 10 MHz
4
5
pF
pd
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈ ꢉꢊ
ꢀ ꢋꢁ ꢌꢍ ꢎꢏ ꢀꢅ ꢆꢆꢍꢐ ꢑ ꢒꢍꢈꢄꢌ ꢎ ꢍꢎ ꢑ ꢎ ꢍ ꢈꢓ ꢄꢁꢀ ꢍꢄꢈꢒ ꢓ
ꢔꢋ ꢈ ꢕ ꢁ ꢋ ꢁꢎ ꢖ ꢒꢁꢗ ꢋ ꢌꢅ ꢓꢄꢘ ꢍꢎ ꢌ ꢄꢈꢎ ꢍꢒ ꢌꢋ ꢖ ꢗ ꢅꢁꢖꢈ ꢋꢒ ꢁ ꢀ
SCES612B – OCTOBER 2004 − −REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
V
= 2.5 V
V
= 3.3 V
CC
0.2 V
CC
0.3 V
C
L
1 MΩ
(see Note A)
C
5, 10, 15, 30 pF 5, 10, 15, 30 pF
V /2 V /2
L
V
MI
I
I
V
MO
V
CC
/2
V
CC
/2
LOAD CIRCUIT
V
I
V
MI
V
MI
Input
0 V
t
t
t
PHL
PLH
V
V
OH
V
MO
V
Mo
Output
OL
t
PHL
PLH
V
V
OH
V
Mo
V
Mo
Output
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
C. The outputs are measured one at a time, with one transition per measurement.
D.
t
and t
PHL
are the same as t .
pd
PLH
Figure 12. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
6
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-3/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
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