SN74AVC16722 [TI]
22-BIT FLIP-FLOP WITH 3-STATE OUTPUTS; 22位触发器具有三态输出
| 型号： | SN74AVC16722 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 22-BIT FLIP-FLOP WITH 3-STATE OUTPUTS |
| 文件： | 总12页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166H – DECEMBER 1998 – REVISED JUNE 2000
Member of the Texas Instruments
Widebus Family
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
I
Supports Partial-Power-Down Mode
off
Operation
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class I
Packaged in Thin Shrink Small-Outline
Package
Dynamic Drive Capability Is Equivalent to
Standard Outputs With I
and I
of
OH
OL
±24 mA at 2.5-V V
CC
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical V vs I and V
vs I
curves to illustrate the output impedance and drive capability of the
OL
OL
OH
OH
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
T
= 25°C
T
= 25°C
A
A
Process = Nominal
Process = Nominal
2.8
2.4
2.0
2.8
2.4
2.0
V
= 3.3 V
CC
1.6
1.2
0.8
0.4
1.6
1.2
0.8
0.4
V
= 2.5 V
CC
V
= 1.8 V
CC
V
= 3.3 V
V
= 2.5 V
CC
CC
V
= 1.8 V
CC
–160 –144 –128 –112 –96 –80 –64 –48 –32 –16
– Output Current – mA
0
17
34
51
68
85 102 119 136 153 170
0
I
– Output Current – mA
I
OH
OL
Figure 1. Output Voltage vs Output Current
This 22-bit flip-flop is operational at 1.2-V to 3.6-V V , but is designed specifically for 1.65-V to 3.6-V V
CC
operation.
CC
The 22 flip-flops of the SN74AVC16722 are edge-triggered D-type flip-flops with clock-enable (CLKEN) input.
On the positive transition of the clock (CLK) input, the device stores data into the flip-flops if CLKEN is low. If
CLKEN is high, no data is stored.
A buffered output-enable (OE) input places the 22 outputs in either a normal logic state (high or low) or the
high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC, EPIC, and Widebus are trademarks of Texas Instruments.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166H – DECEMBER 1998 – REVISED JUNE 2000
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16722 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG PACKAGE
(TOP VIEW)
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OE
Q1
Q2
GND
Q3
Q4
CLK
D1
D2
GND
D3
D4
2
3
4
5
6
7
V
V
CC
CC
8
Q5
Q6
Q7
GND
Q8
D5
D6
D7
GND
D8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Q9
D9
Q10
Q11
Q12
Q13
GND
Q14
Q15
Q16
D10
D11
D12
D13
GND
D14
D15
D16
V
V
CC
CC
Q17
Q18
GND
Q19
Q20
D17
D18
GND
D19
D20
V
V
CC
CC
Q21
Q22
GND
NC
D21
D22
GND
CLKEN
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166H – DECEMBER 1998 – REVISED JUNE 2000
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLKEN CLK
D
X
H
L
H
L
L
L
X
X
Q
0
L
↑
↑
H
L
L
L
L or H
X
X
X
Q
0
H
Z
logic diagram (positive logic)
1
OE
64
CLK
33
CE
C1
1D
CLKEN
2
63
Q1
D1
To 21 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W
IK
I
Output clamp current, I
OK
O
O
Continuous current through each V
CC
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166H – DECEMBER 1998 – REVISED JUNE 2000
recommended operating conditions (see Note 4)
MIN
1.4
MAX
UNIT
Operating
3.6
V
Supply voltage
V
CC
IH
Data retention only
1.2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2 V
V
CC
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 1.2 V
0.65 × V
CC
V
High-level input voltage
0.65 × V
V
V
CC
1.7
2
GND
0.35 × V
0.35 × V
0.7
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
CC
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
0
3.6
V
V
I
Active state
3-state
V
CC
3.6
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
–2
–4
–8
†
I
Static high-level output current
mA
mA
OHS
OLS
–12
2
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
4
†
I
Static low-level output current
8
12
5
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
= 1.4 V to 3.6 V
ns/V
T
–40
85
°C
A
†
DynamicdrivecapabilityisequivalenttostandardoutputswithI
OH
andI of±24mAat2.5-VV .SeeFigure1forV vsI andV vs I
OL CC OL OL OH OH
characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and
Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166H – DECEMBER 1998 – REVISED JUNE 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
= –100 µA
MIN
–0.2
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
1.4 V to 3.6 V
1.4 V
V
CC
OHS
OHS
OHS
OHS
OHS
OLS
OLS
OLS
OLS
OLS
= –2 mA,
= –4 mA,
= –8 mA,
= –12 mA,
= 100 µA
= 2 mA,
V
V
V
V
= 0.91 V
= 1.07 V
= 1.7 V
= 2 V
1.05
1.2
IH
IH
IH
IH
V
1.65 V
2.3 V
V
OH
OL
1.75
2.3
3 V
1.4 V to 3.6 V
1.4 V
0.2
0.4
V
IL
V
IL
V
IL
V
IL
= 0.49 V
= 0.57 V
= 0.7 V
= 0.8 V
V
= 4 mA,
1.65 V
2.3 V
0.45
0.55
0.7
V
= 8 mA,
= 12 mA,
3 V
I
I
I
I
V = V or GND
CC
3.6 V
±2.5
±10
±10
40
µA
µA
µA
µA
I
I
V or V = 3.6 V
0
off
I
O
V
O
= V or GND
CC
3.6 V
OZ
CC
V = V
I
or GND,
I = 0
O
3.6 V
CC
2.5 V
4
4
2
2
Control inputs
Data inputs
Outputs
3.3 V
C
C
V = V
or GND
pF
pF
i
I
CC
2.5 V
3.3 V
2.5 V
6.5
6
V
O
= V
or GND
CC
o
3.3 V
†
Typical values are measured at T = 25°C.
A
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.1 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
= 1.2 V
MAX
CC
UNIT
MIN
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
Clock frequency
80
140
175
MHz
ns
clock
Pulse duration, CLK high or low
6.2
5.7
1.6
0
3.5
3.5
1.4
0
2.8
2.5
1.4
0
w
Data before CLK↑
Setup time
12.8
3.5
0
8.3
2
t
ns
ns
su
h
CLKEN before CLK↑
Data after CLK↑
Hold time
0
t
CLKEN after CLK↑
2.1
1.6
1.3
1.2
1.2
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.1 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
CC
= 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN
MAX
MIN
MAX
80
MIN
MAX
140
3.3
6
MIN
MAX
175
2.6
f
t
t
t
MHz
ns
max
CLK
OE
Q
Q
Q
7.7
1.5
2.5
1.9
6.3
10.6
7.2
1.5
2.4
1.9
5.4
9.5
7
1
1.8
1.2
0.7
1.4
1.2
pd
11.2
6.8
4.3
ns
en
3.6
3.4
ns
OE
dis
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166H – DECEMBER 1998 – REVISED JUNE 2000
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
= 2.5 V
CC
TYP
V
= 3.3 V
CC
TYP
PARAMETER
TEST CONDITIONS
UNIT
Outputs enabled
Outputs disabled
88
60
98
64
110
79
Power dissipation
capacitance
C
C
= 0, f = 10 MHz
L
pF
pd
PARAMETER MEASUREMENT INFORMATION
= 1.2 V AND 1.5 V ± 0.1 V
V
CC
2 × V
CC
Open
S1
2 kΩ
From Output
Under Test
TEST
S1
Open
2 × V
GND
t
pd
/t
C
= 15 pF
t
L
PLZ PZL
CC
GND
2 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
CC
/2
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
+ 0.1 V
OL
CC
V
0 V
OL
t
t
PZH
PHZ
– 0.1 V
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
V
CC
/2
Output
V
CC
/2
V
/2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166H – DECEMBER 1998 – REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
S1
1 kΩ
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
1 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 3. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166H – DECEMBER 1998 – REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
GND
S1
500 Ω
From Output
Under Test
TEST
S1
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 4. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16722
22-BIT FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES166H – DECEMBER 1998 – REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
= 3.3 V ± 0.3 V
V
CC
2 × V
CC
Open
GND
TEST
S1
S1
500 Ω
From Output
Under Test
t
Open
pd
t
/t
2 × V
CC
GND
PLZ PZL
/t
t
C
= 30 pF
PHZ PZH
L
500 Ω
(see Note A)
t
LOAD CIRCUIT
w
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
Timing
Input
0 V
V
/2
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Data
Input
Output
V
CC
V
CC
/2
V
CC
/2
Control
(low-level
enabling)
0 V
V
CC
/2
V
CC
/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
CC
/2
S1 at 2 × V
(see Note B)
Input
V
CC
/2
V
CC
/2
V
OL
+ 0.3 V
CC
V
OL
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.3 V
OH
V
CC
/2
V
CC
/2
Output
V
CC
/2
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 5. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
74AVC16722DGGRE4
SN74AVC16722DGGR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
64
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
DGG
64
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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