SN74AVC24T245NMUR_技术文档

SN74AVC24T245

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SCES552E – FEBRUARY 2004 – REVISED AUGUST 2020

24-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation And 3-

State Outputs

direction-control (DIR) input. The output-enable ( OE)

input can be used to disable the outputs so the buses

1 Features

•

Control Inputs V_IH/V_ILLevels Are Referenced to

V_CCAVoltage

are effectively isolated.

The SN74AVC24T245 is designed so that the control

pins (1DIR, 2DIR, 3DIR, 4DIR, 5DIR, 6DIR, 1 OE, 2

OE, 3 OE, 4 OE, 5 OE, and 6 OE) are supplied by

V_CCIsolation Feature – If Either V_CCInput Is at

GND, All Outputs Are in the High-Impedance State

Overvoltage-Tolerant Inputs/Outputs Allow Mixed-

Voltage-Mode Data Communications

Fully Configurable Dual-Rail Design Allows Each

Port to Operate Over Full 1.2-V to 3.6-V Power-

Supply Range

I_offSupports Partial-Power-Down Mode Operation

I/Os Are 4.6-V Tolerant

Max Data Rates

– 380 Mbps (1.8-V to 3.3-V Translation)

– 200 Mbps (<1.8-V to 3.3-V Translation)

– 200 Mbps (Translate to 2.5 V or 1.8 V)

– 150 Mbps (Translate to 1.5 V)

– 100 Mbps (Translate to 1.2 V)

Latch-Up Performance Exceeds 100 mA Per JESD

78, Class II

V_CCA

.

This device is fully specified for partial-power-down

applications using I_off. The I_offcircuitry disables the

outputs, preventing damaging current backflow

through the device when it is powered down.

•

The V_CCisolation feature ensures that if either V_CC

input is at GND, then both ports are in the high-

impedance state.

To ensure the high-impedance state during power up

or power down, OE should be tied to V_CCAthrough a

pullup resistor; the minimum value of the resistor is

determined by the current-sinking capability of the

driver.

•

Device Information

PART NUMBER

PACKAGE⁽¹⁾BODY SIZE (NOM)

ESD Protection Exceeds JESD 22

– 8000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

10.00 mm × 4.50

mm

SN74AVC24T245GRG/ZRG LFBGA

SN74AVC24T245NMU nFBGA

10.00 mm × 4.50

mm

2 Applications

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

Personal Electronics

Industrial

Enterprise

P5

P6

2DIR

1DIR

A6

A5

1OE

2OE

D6

B6

1A1

2A1

Telecom

D1

B1

1B1

2B1

3 Description

To Three Other Channels

P3

P4

4DIR

3DIR

This 24-bit noninverting bus transceiver uses two

separate configurable power-supply rails. The

SN74AVC24T245 is optimized to operate with V_CCA

V_CCBset at 1.4 V to 3.6 V. It is operational with

V_CCA/V_CCBas low as 1.2 V. The A port is designed to

track V_CCA. V_CCAaccepts any supply voltage from 1.2

V to 3.6 V. The B port is designed to track V_CCB. V_CCB

accepts any supply voltage from 1.2 V to 3.6 V. This

allows for universal low-voltage bidirectional

translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-

V, and 3.3-V voltage nodes.

A4

A3

3OE

4OE

H6

F6

3A1

4A1

/

H1

F1

4B1

3B1

P1

P2

6DIR

5DIR

A2

A1

5OE

6OE

M6

K6

6A1

5A1

M1

K1

6B1

5B1

Figure 3-1. Logic Diagram

The SN74AVC24T245 is designed for asynchronous

communication between data buses. The device

transmits data from the A bus to the B bus or from the

B bus to the A bus, depending on the logic level at the

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................7

6.4 Thermal Information....................................................8

6.5 Electrical Characteristics.............................................9

6.6 Switching Characteristics..........................................10

6.7 Switching Characteristics..........................................10

6.8 Switching Characteristics..........................................11

6.9 Switching Characteristics..........................................11

6.10 Switching Charactertistics.......................................12

6.11 Operating Characteristics........................................12

6.12 Typical Characteristics............................................13

7 Parameter Measurement Information..........................15

8 Detailed Description......................................................16

8.1 Overview...................................................................16

8.2 Functional Block Diagram.........................................16

8.3 Feature Description...................................................17

8.4 Device Functional Modes..........................................17

9 Application and Implementation..................................18

9.1 Application Information............................................. 18

9.2 EnableTimes............................................................. 18

9.3 Typical Application.................................................... 19

10 Power Supply Recommendations..............................21

11 Layout...........................................................................21

11.1 Layout Guidelines................................................... 21

11.2 Layout Example...................................................... 21

12 Device and Documentation Support..........................22

12.1 Documentation Support.......................................... 22

12.2 Related Documentation.......................................... 22

12.3 Trademarks.............................................................22

12.4 Electrostatic Discharge Caution..............................22

12.5 Glossary..................................................................22

13 Mechanical, Packaging, and Orderable

Information.................................................................... 22

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (August 2005) to Revision E (August 2020)

Page

•

Updated document to current TI data sheet format............................................................................................1

Removed Ordering Information table..................................................................................................................1

Added Applications list, Device Information table...............................................................................................1

Added NMU package option to Device Information table...................................................................................1

Added NMU package to pinout drawing............................................................................................................. 3

Added ESD Ratings table...................................................................................................................................6

Added Thermal Information table....................................................................................................................... 8

Added NMU package to Thermal Information table............................................................................................8

Added Typical Characteristics section..............................................................................................................13

Added Detailed Description section..................................................................................................................16

Added Application and Implementation section................................................................................................18

Added Power Supply Recommendations section.............................................................................................21

Added Layout section....................................................................................................................................... 21

Added Device and Documentation Support section......................................................................................... 22

Added Mechanical, Packaging, and Orderable Information section.................................................................22

2

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5 Pin Configuration and Functions

1

2

3

4

5

6

A

B

C

D

E

F

G

H

J

K

L

M

N

P

Figure 5-1. GRG/ZRG, NMU Package 83-Pin LFBGA, nFBGA Top View

Table 5-1. Pin Assignments

1

2

3

4

5

6

A

B

C

D

E

F

6 OE

1B1

1B3

2B1

2B3

3B1

3B3

4B1

4B3

5B1

5B3

6B1

6B3

6DIR

5 OE

1B2

1B4

2B2

2B4

3B2

3B4

4B2

4B4

5B2

5B4

6B2

6B4

5DIR

4 OE

V_CCB

GND

V_CCB

GND

3 OE

V_CCA

GND

V_CCA

GND

V_CCA

GND

V_CCA

GND

V_CCA

3DIR

2 OE

1A2

1A4

2A2

2A4

3A2

3A4

4A2

4A4

5A2

5A4

6A2

6A4

2DIR

1 OE

1A1

1A3

2A1

2A3

3A1

3A3

4A1

4A3

5A1

5A3

6A1

6A3

1DIR

G

H

J

V_CCB

GND

V_CCB

GND

V_CCB

4DIR

K

L

M

N

P

Table 5-2. Pin Functions

I/O

DESCRIPTION

NO.

NAME

Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State

A1

A2

A3

A4

6 OE

5 OE

4 OE

3 OE

Input

mode. Referenced to V_CCA

Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State

mode. Referenced to V_CCA

Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State

mode. Referenced to V_CCA

.

Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State

mode. Referenced to V_CCA

.

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Table 5-2. Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State

A5

2 OE

Input

mode. Referenced to V_CCA

.

Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State

mode. Referenced to V_CCA

A6

1 OE

.

B1

B2

B3

B4

B5

B6

C1

C2

C3

C4

C5

C6

D1

D2

D3

D4

D5

D6

E1

E2

E3

E4

E5

E6

F1

F2

F3

F4

F5

F6

G1

G2

G4

G5

G6

H1

H2

H3

H4

H5

H6

1B1

1B2

V_CCB

V_CCA

1A2

1A1

1B3

1B4

GND

1A4

1A3

2B1

2B2

V_CCB

V_CCA

2A2

2A1

2B3

2B4

GND

2A4

2A3

3B1

3B2

GND

3A2

3A1

3B3

3B4

GND

3A4

3A3

4B1

4B2

V_CCB

V_CCA

4A2

4A1

Input/Output

—

Referenced to V_CCB

.

B-port supply voltage. 1.2 V ≤ V_CCB≤ 3.6 V.

A-port supply voltage. 1.2 V ≤ V_CCA≤ 3.6 V.

—

Input/Output

—

Referenced to V_CCA

Referenced to V_CCB

Ground.

.

—

Ground.

Input/Output

—

Referenced to V_CCA

Referenced to V_CCB

.

B-port supply voltage. 1.2 V ≤ V_CCB≤ 3.6 V.

A-port supply voltage. 1.2 V ≤ V_CCA≤ 3.6 V.

—

Input/Output

—

Referenced to V_CCA

Referenced to V_CCB

Ground.

.

—

Ground.

Input/Output

—

Referenced to V_CCA

Referenced to V_CCB

Ground.

.

—

Ground.

Input/Output

—

Referenced to V_CCA

Referenced to V_CCB

Ground.

.

Input/Output

—

Referenced to V_CCA

Referenced to V_CCB

.

B-port supply voltage. 1.2 V ≤ V_CCB≤ 3.6 V.

A-port supply voltage. 1.2 V ≤ V_CCA≤ 3.6 V.

—

Input/Output

Referenced to V_CCA

.

4

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Table 5-2. Pin Functions (continued)

I/O

DESCRIPTION

NO.

J1

NAME

4B3

Input/Output

—

Referenced to V_CCB

Ground.

.

J2

4B4

J3

GND

4A4

J4

—

Ground.

J5

Input/Output

—

Referenced to V_CCA

Referenced to V_CCB

Ground.

.

J6

4A3

K1

K2

K3

K4

K5

K6

L1

5B1

5B2

GND

5A2

—

Ground.

Input/Output

—

Referenced to V_CCA

Referenced to V_CCB

.

5A1

5B3

L2

5B4

L3

V_CCB

V_CCA

5A4

B-port supply voltage. 1.2 V ≤ V_CCB≤ 3.6 V.

A-port supply voltage. 1.2 V ≤ V_CCA≤ 3.6 V.

L4

—

L5

Input/Output

—

Referenced to V_CCA

Referenced to V_CCB

Ground.

.

L6

5A3

M1

M2

M3

M4

M5

M6

N1

N2

N3

N4

N5

N6

P1

P2

P3

P4

P5

P6

6B1

6B2

GND

6A2

—

Ground.

Input/Output

—

Referenced to V_CCA

Referenced to V_CCB

.

6A1

6B3

6B4

V_CCB

V_CCA

6A4

B-port supply voltage. 1.2 V ≤ V_CCB≤ 3.6 V.

A-port supply voltage. 1.2 V ≤ V_CCA≤ 3.6 V.

—

Input/Output

Input

Referenced to V_CCA

.

6A3

6DIR

5DIR

4DIR

3DIR

2DIR

1DIR

Direction-control signal. Referenced to V_CCA

.

Input

Direction-control signal. Referenced to V_CCA.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX UNIT

V_CCA

Supply voltage range

V_CCB

–0.5

4.6

V

I/O ports (A port)

I/O ports (B port)

Control inputs

A port

–0.5

4.6

V_I

Input voltge range⁽²⁾

V

Voltage range applied to any output

V_O

V

in the high-impedance or power-off state⁽²⁾

B port

A port

–0.5 V_CCA+ 0.5

Voltage range applied to any output in the high or low state^{(2) (3)}

B port

–0.5 V_CCB+ 0.5

I_IK

I_OK

I_O

Input clamp current

V_I< 0

–50

mA

°C

Output clamp current

V_O< 0

Continuous output current

±50

Continuous current through each V_CCA, V_CCB, and GND

Storage temperature range

±100

T_stg

–65

150

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The output positive-voltage rating may be exceeded up to 4.6-V maximum if the output current rating is observed.

6.2 ESD Ratings

VALUE

±8000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001¹

V _(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101²

6

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6.3 Recommended Operating Conditions

(1) (2) (3)

V_CCI

V_CCO

MIN

MAX UNIT

V_CCA

V_CCB

Supply voltage

1.2

3.6

V

1.2

1.2 V to 1.95 V

1.95 V to 2.7 V

2.7 V to 3.6 V

1.2 V to 1.95 V

1.95 V to 2.7 V

2.7 V to 3.6 V

1.2 V to 1.95 V

1.95 V to 2.7 V

2.7 V to 3.6 V

1.2 V to 1.95 V

1.95 V to 2.7 V

2.7 V to 3.6 V

V_CCI× 0.65

High-level

input voltage

V_IH

V_IL

V_IH

V_IL

Data inputs⁽⁴⁾

1.6

2

V

V_CCI× 0.35

Low-level

input voltage

0.7

0.8

V_CCA× 0.65

High-level

input voltage

DIR

1.6

2

(5)

(referenced to V_CCA

)

V_CCA× 0.35

Low-level

input voltage

DIR

0.7

0.8

3.6

V_CCO

3.6

–3

–6

–8

–9

–12

3

(referenced to V_CCA

)

V_I

Input voltage

0

V

Active state

3-state

V_O

Output voltage

1.2 V

1.4 V to 1.6 V

1.65 V to 1.95 V

2.3 V to 2.7 V

3 V to 3.6 V

1.2 V

I_OH

High-level output current

Low-level output current

mA

1.4 V to 1.6 V

1.65 V to 1.95 V

2.3 V to 2.7 V

3 V to 3.6 V

6

I_OL

8

9

12

5

Δt/Δv

T_A

Input transition rise or fall rate

Operating free-air temperature

ns/V

°C

–40

85

(1) V_CCIis the V_CCassociated with the data input port.

(2) V_CCOis the V_CCassociated with the output port.

(3) All unused data inputs of the device must be held at V_CCIor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(4) For V_CCIvalues not specified in the data sheet, V_IHmin = V_CCI× 0.7 V, V_ILmax = V_CCI× 0.3 V.

(5) For V_CCIvalues not specified in the data sheet, V_IHmin = V_CCA× 0.7 V, V_ILmax = V_CCA× 0.3 V.

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6.4 Thermal Information

SN74AVC24T245

THERMAL METRIC⁽¹⁾

GRG

83

ZRG

83

NMU

83

UNIT

R _θJA

Junction-to-ambient thermal resistance

38.1

44.3

°C/W

Junction-to-case (top) thermal

resistance

R _θJC(top)

R _θJB

22.8

17.0

0.44

22.8

17.0

0.44

24.5

29.1

0.5

Junction-to-board thermal resistance

Junction-to-top characterization

parameter

ψ _JT

Junction-to-board characterization

parameter

ψ _JB

16.9

29.2

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application

report.

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)^{(2) (3)}

T_A= 25°C

–40°C to 85°C

PARAMETER

TEST CONDITIONS

V_CCA

V_CCB

UNIT

MIN

TYP

MAX

MIN

MAX

I_OH= –100 μA

1.2 V to 3.6 V 1.2 V to 3.6 V

V_CCO– 0.2

I_OH= –3 mA

I_OH= –6 mA

I_OH= –8 mA

I_OH= –9 mA

I_OH= –12 m

I_OL= 100 μA

I_OL= 3 mA

I_OL= 6 mA

I_OL= 8 mA

I_OL= 9 mA

I_OL= 12 mA

1.2 V

1.4 V

1.65 V

2.3 V

3 V

1.2 V

1.4 V

1.65 V

2.3 V

3 V

0.95

1.05

1.2

V_OH

V_I= V_IH

V

1.75

2.3

1.2 V to 3.6 V 1.2 V to 3.6 V

0.2

1.2 V

1.4 V

1.65 V

2.3 V

3 V

1.2 V

1.4 V

1.65 V

2.3 V

3 V

0.15

0.35

0.45

0.55

0.7

V_OL

V_I= V_IL

V

Control

inputs

I_I

V_I= V_CCAor GND

1.2 V to 3.6 V 1.2 V to 3.6 V

±0.025 ±0.25

±1

±5

μA

A or B

port

0 V

0 to 3.6 V

0 V

±0.1

±2.5

I_off

V_Ior V_O= 0 to 3.6 V

A or B

port

0 to 3.6 V

V_O= V_CCOor GND,

V_I= V_CCIor GND,

OE = V_IH

A or B

port

(1)

I_OZ

3.6 V

±0.5

±2.5

±5

μA

1.2 V to 3.6 V 1.2 V to 3.6 V

40

–5

40

–5

V_I= V_CCIor GND,

I_O= 0

I_CCA

0 V

3.6 V

0 V

3.6 V

1.2 V to 3.6 V 1.2 V to 3.6 V

V_I= V_CCIor GND,

I_O= 0

I_CCB

0 V

3.6 V

0 V

μA

3.6 V

V_I= V_CCIor GND,

I_O= 0

I_CCA+ I_CCB

1.2 V to 3.6 V 1.2 V to 3.6 V

75

μA

pF

Control

inputs

C_i

V_I= 3.3 V or GND

V_O= 3.3 V or GND

3.3 V

3.5

7

A or B

port

C_io

(1) For I/O ports, the parameter I_OZincludes the input leakage current.

(2) V_CCOis the V_CCassociated with the output port.

(3) V_CCIis the V_CCassociated with the input port.

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6.6 Switching Characteristics

over recommended operating free-air temperature range, V_CCA= 1.2 V (see Figure 7-1)

V_CCB= 1.2 V

V_CCB= 1.5 V

V_CCB= 1.8 V

V_CCB= 2.5 V

TYP

2.8

V_CCB= 3.3 V

TYP

3.2

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

ns

TYP

4.1

4.4

6.4

6

TYP

3.3

4

TYP

3

t_PLH

t_PHL

t_PLH

t_PHL

t_PZH

t_PZL

t_PZH

t_PZL

t_PHZ

t_PLZ

t_PHZ

t_PLZ

A

B

A

B

A

B

3

2.8

3.2

3.8

6.4

4

3.6

3.5

B

ns

4

3.6

3.5

6.4

4.6

6.6

4.9

6.4

OE

ns

6.4

3.4

3.2

ns

6

4

3.4

3.2

6.6

6

6.6

4.9

6.6

6.8

ns

6.6

6.8

4.2

5.3

ns

6

4.2

5.3

6.7 Switching Characteristics

over recommended operating free-air temperature range, V_CCA= 1.5 V ± 0.1 V (see Figure 7-1)

V_CCB= 1.5 V V_CCB= 1.8 V V_CCB= 2.5 V V_CCB= 3.3 V

V_CCB= 1.2 V

FROM

(INPUT)

TO

(OUTPUT)

± 0.1 V

± 0.15 V

± 0.2 V

± 0.3 V

PARAMETER

UNIT

TYP

3.6

3.3

4.3

5.6

4.5

5.5

MIN MAX

t_PLH

t_PHL

t_PLH

t_PHL

t_PZH

t_PZL

t_PZH

t_PZL

t_PHZ

t_PLZ

t_PHZ

t_PLZ

0.5

1

6.2

0.5

1

5.2

0.5

1

4.1

0.5

1

3.7

A

B

A

B

A

B

ns

6.2

5.9

5.6

5.5

B

6.2

5.9

5.6

5.5

10.1

9.1

10.1

8.1

10.1

5.9

10.1

5.2

OE

1

0.5

1.5

0.5

1.5

1

0.5

1.5

1

8.1

5.9

5.2

1.5

9.1

8.7

7.5

6.5

6.3

8.7

7.5

1

6.5

1

6.3

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6.8 Switching Characteristics

over recommended operating free-air temperature range, V_CCA= 1.8 V ± 0.15 V (see Figure 7-1)

V_CCB= 1.5 V V_CCB= 1.8 V V_CCB= 2.5 V V_CCB= 3.3 V

V_CCB= 1.2 V

FROM

(INPUT)

TO

(OUTPUT)

± 0.1 V

± 0.15 V

± 0.2 V

± 0.3 V

PARAMETER

UNIT

TYP

3.4

3

MIN MAX

t_PLH

t_PHL

t_PLH

t_PHL

t_PZH

t_PZL

t_PZH

t_PZL

t_PHZ

t_PLZ

t_PHZ

t_PLZ

0.5

1

5.9

5.2

7.8

9.2

7.7

8.4

0.5

1

4.8

7.8

7.4

7.7

7.1

0.5

1

3.7

4.5

7.8

5.3

7.7

5.9

0.5

1

3.3

4.4

7.8

4.5

7.7

5.7

A

B

A

B

A

B

ns

B

3

3.4

5.4

4.2

5.2

OE

1

0.5

1.5

0.5

1.5

1

0.5

1.5

1

1.5

1

6.9 Switching Characteristics

over recommended operating free-air temperature range, V_CCA= 2.5 V ± 0.2 V (see Figure 7-1)

V_CCB= 1.5 V V_CCB= 1.8 V V_CCB= 2.5 V V_CCB= 3.3 V

V_CCB= 1.2 V

FROM

(INPUT)

TO

(OUTPUT)

± 0.1 V

± 0.15 V

± 0.2 V

± 0.3 V

PARAMETER

UNIT

TYP

3.2

2.6

2.5

5.2

3

MIN MAX

t_PLH

t_PHL

t_PLH

t_PHL

t_PZH

t_PZL

t_PZH

t_PZL

t_PHZ

t_PLZ

t_PHZ

t_PLZ

0.5

1

5.6

4.1

5.3

9.4

6.1

7.9

0.5

1

4.5

3.7

5.3

7.3

6.1

6.6

0.5

1

3.3

5.3

5.1

6.1

0.5

1

2.8

3.2

5.3

4.5

6.1

5.2

A

B

A

B

A

B

ns

B

OE

3

1

5

1

5

1

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6.10 Switching Charactertistics

over recommended operating free-air temperature range, V_CCA= 3.3 V ± 0.3 V (see Figure 7-1)

V_CCB= 1.5 V V_CCB= 1.8 V V_CCB= 2.5 V V_CCB= 3.3 V

V_CCB= 1.2 V

FROM

(INPUT)

TO

(OUTPUT)

± 0.1 V

± 0.15 V

± 0.2 V

± 0.3 V

PARAMETER

UNIT

TYP

3.2

2.8

2.2

5.1

3.4

4.9

MIN MAX

t_PLH

t_PHL

t_PLH

t_PHL

t_PZH

t_PZL

t_PZH

t_PZL

t_PHZ

t_PLZ

t_PHZ

t_PLZ

0.5

1

5.5

3.7

4.3

9.3

5

0.5

1

4.4

3.3

4.2

7.2

5

0.5

1

3.2

2.8

4.1

4.9

5

0.5

2.7

4

A

B

A

B

A

B

ns

B

OE

4

5

7.7

6.5

5.2

5

1

5

6.11 Operating Characteristics

V_CCAand V_CCB= 3.3 V, T_A= 25°C

V_CCA

=

V_CCA

=

V_CCA

=

V_CCA

=

V_CCA=

TEST

CONDITIONS

V_CCB= 1.5 V V_CCB= 1.2 V V_CCB= 1.8 V V_CCB= 2.5 V V_CCB= 3.3 V

PARAMETER

UNIT

TYP

Outputs

enabled

1

2

A to B

B to A

A to B

B to A

Outputs

disabled

1

19

1

19

1

20

1

21

1

2

22

1

C_L= 0,

f = 10 MHz,

t_r= t_f= 1 ns

(1)

C_pdA

pF

Outputs

enabled

Outputs

disabled

Outputs

enabled

19

1

19

1

20

1

21

1

22

1

Outputs

disabled

C_L= 0,

f = 10 MHz,

t_r= t_f= 1 ns

(1)

C_pdB

pF

Outputs

enabled

1

2

Outputs

disabled

1

2

(1) Power dissipation capacitance per transceiver

12

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6.12 Typical Characteristics

6

5

4

3

2

1

0

T

= 25°C

T

A

= 25°C

A

V

= 1.2 V

V

CCA

= 1.2 V

CCA

5

4

3

2

1

0

V

= 1.2 V

= 1.5 V

= 1.8 V

= 2.5 V

= 3.3 V

V

= 1.2 V

= 1.5 V

= 1.8 V

= 2.5 V

= 3.3 V

CCB

V

CCB

0

10

20

30

40

− Load Capacitance − pF

50

60

0

10

20

30

40

50

60

C

L

C

L

− Load Capacitance − pF

Figure 6-1. Propagation Delay vs Load

Capacitance

Figure 6-2. Propagation Delay vs Load

Capacitance

6

T = 25°C

A

T

A

= 25°C

V = 1.5 V

CCA

V

CCA

= 1.5 V

5

4

3

2

1

0

5

4

3

2

1

0

V

= 1.2 V

= 1.5 V

= 1.8 V

= 2.5 V

= 3.3 V

CCB

V

= 1.2 V

= 1.5 V

= 1.8 V

= 2.5 V

= 3.3 V

CCB

V

CCB

V

CCB

0

10

20

30

40

50

60

0

10

20

30

40

50

60

C

L

− Load Capacitance − pF

C

L

− Load Capacitance − pF

Figure 6-3. Typical Propagation Delay t_PLH(A to B)

vs Load Capacitance

Figure 6-4. Typical Propagation Delay t_PLH(A to B)

vs Load Capacitance

6

T

A

= 25°C

T

A

= 25°C

V

CCA

= 1.8 V

V

CCA

= 1.8 V

5

4

3

2

1

0

5

4

3

2

1

0

V

= 1.2 V

= 1.5 V

= 1.8 V

= 2.5 V

= 3.3 V

V

= 1.2 V

= 1.5 V

= 1.8 V

= 2.5 V

= 3.3 V

CCB

V

CCB

0

10

20

30

40

50

60

0

10

20

30

40

50

60

C

L

− Load Capacitance − pF

C

L

− Load Capacitance − pF

Figure 6-6. Typical Propagation Delay t_PLH(A to B)

vs Load Capacitance

Figure 6-5. Typical Propagation Delay t_PLH(A to B)

vs Load Capacitance

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6

5

T

= 25°C

T

= 25°C

A

V

= 1.2 V

= 1.5 V

= 1.8 V

= 2.5 V

= 3.3 V

CCB

V

= 2.5 V

V

= 2.5 V

CCA

V

CCB

5

4

3

2

1

0

4

3

2

1

0

V

= 1.2 V

= 1.5 V

= 1.8 V

= 2.5 V

= 3.3 V

CCB

V

CCB

0

10

20

30

40

50

60

0

10

20

30

40

50

60

C

L

− Load Capacitance − pF

C

L

− Load Capacitance − pF

Figure 6-8. Typical Propagation Delay t_PLH(A to B)

vs Load Capacitance

Figure 6-7. Typical Propagation Delay t_PLH(A to B)

vs Load Capacitance

6

T

A

= 25°C

T

= 25°C

A

V

= 1.2 V

= 1.5 V

= 1.8 V

= 2.5 V

= 3.3 V

CCB

V

CCA

= 3.3 V

V

= 3.3 V

CCA

V

CCB

5

4

3

2

1

0

5

4

3

2

1

0

V

= 1.2 V

= 1.5 V

= 1.8 V

= 2.5 V

= 3.3 V

CCB

V

CCB

0

10

20

30

40

50

60

0

10

20

30

40

50

60

C

L

− Load Capacitance − pF

C

L

− Load Capacitance − pF

Figure 6-9. Typical Propagation Delay t_PLH(A to B)

vs Load Capacitance

Figure 6-10. Propagation Delay vs Load

Capacitance

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7 Parameter Measurement Information

2 × V

CCO

TEST

S1

R

L

Open

GND

t

Open

pd

From Output

Under Test

t

/t

PLZ PZL

2 × V

CCO

t /t

PHZ PZH

GND

C

L

(see Note A)

R

L

t

w

LOAD CIRCUIT

V

CCI

V

CCI

/2

V

CCI

/2

Input

C

L

V

TP

R

L

V

CCO

0 V

1.5 V 0.1 V

2 kΩ

0.1 V

0.15 V

0.3 V

15 pF

VOLTAGE WAVEFORMS

PULSE DURATION

1.8 V 0.15 V

2.5 V 0.2 V

3.3 V 0.3 V

V

CCA

Output

Control

(low-level

enabling)

V /2

CCA

V

CCA

/2

t

0 V

t

PZL

PLZ

V

CCO

Output

V

CCI

V

/2

Waveform 1

S1 at 2 × V

CCO

Input

V

CCI

/2

V

CCI

/2

V

+ V

OL

TP

CCO

(see Note B)

OL

0 V

t

PZH

PHZ

t

PHL

PLH

Output

Waveform 2

S1 at GND

V

OH

V

OH

V

OH

− V

TP

V

CCO

Output

V /2

CCO

V

CCO

/2

(see Note B)

0 V

V

OL

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PROPAGATION DELAY TIMES

NOTES: A. C includes probe and jig capacitance.

L

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns.

O

D. The outputs are measured one at a time, with one transition per measurement.

E.

F.

G.

H.

I.

t

and t

are the same as t

.

dis

PLZ

PZL

PLH

PHZ

are the same as t

.

PZH

en

and t

are the same as t .

pd

PHL

V

is the V associated with the input port.

CC

is the V associated with the output port.

CCI

CCO

CC

Figure 7-1. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview

The SN74AVC24T245 is a 16-bit, dual-supply noninverting bidirectional voltage level translation. Pins A and

control pins (DIR and OE) are supported by V_CCAand pins B are supported by V_CCB. The A port can accept I/O

voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.2 V to 3.6 V. A high on DIR

allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to

low. When OE is set to high, both A and B are in the high-impedance state.

This device is fully specified for partial-power-down applications using off output current (I_off).

The V_CCisolation feature ensures that if either V_CCinput is at GND, both ports are put in a high-impedance

state.

8.2 Functional Block Diagram

P5

P6

2DIR

1DIR

A6

A5

1OE

2OE

D6

B6

1A1

2A1

D1

B1

2B1

1B1

To Three Other Channels

P3

P4

4DIR

3DIR

A4

A3

3OE

4OE

H6

F6

4A1

3A1

H1

F1

4B1

3B1

P1

P2

6DIR

5DIR

A2

A1

5OE

6OE

M6

K6

6A1

5A1

M1

K1

6B1

5B1

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8.3 Feature Description

8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-

Supply Range

Both V_CCAand V_CCBcan be supplied at any voltage from 1.2 V to 3.6 V which makes the device suitable for

translating between any of the low voltage nodes (1.2 V, 1.8 V, 2.5 V, and 3.3 V).

8.3.2 Partial-Power-Down Mode Operation

This device is fully specified for partial-power-down applications using off output current (I_off). The I_offcircuitry will

prevent backflow current by disabling I/O output circuits when device is in partial power-down mode.

8.3.3 V_CCIsolation

The V_CCisolation feature ensures that if either V_CCAor V_CCBare at GND, both ports will be in a high-impedance

state (I_OZ). This prevents false logic levels from being presented to either bus.

8.4 Device Functional Modes

The SN74AVC24T245 is a voltage level translator that can operate from 1.2 V to 3.6 V (V_CCA) and 1.2 V to 3.6 V

(V_CCB). The signal translation between 1.2 V and 3.6 V requires direction control and output enable control.

When OE is low and DIR is high, data transmission is from A to B. When OE is low and DIR is low, data

transmission is from B to A. When OE is high, both output ports will be high-impedance.

Table 8-1. Function Table

(Each 4-Bit Section)

INPUTS

OPERATION

OE

DIR

B data to A

bus

L

A data to B

bus

L

H

X

H

Isolation

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The SN74AVC24T245 device can be used in level-shifting applications for interfacing devices and addressing

mixed voltage incompatibility. The SN74AVC24T245 device is ideal for data transmission where direction is

different for each channel.

9.2 EnableTimes

Calculate the enable times for the SN74AVC24T245 using the following formulas:

t_PZH(DIR to A) = t_PLZ(DIR to B) + t_PLH(B to A)

t_PZL(DIR to A) = t_PHZ(DIR to B) + t_PHL(B to A)

t_PZH(DIR to B) = t_PLZ(DIR to A) + t_PLH(A to B)

t_PZL(DIR to B) = t_PHZ(DIR to A) + t_PHL(A to B)

(1)

(2)

(3)

(4)

In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is

switched until an output is expected. For example, if the SN74AVC24T245 initially is transmitting from A to B,

then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the

B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified

propagation delay.

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9.3 Typical Application

1.8 V

3.3 V

0.1 µF

V

CCB

CCA

1DIR/2DIR/3DIR/

4DIR/5DIR/6DIR

1OE/2OE/3OE/

4OE/5OE/6OE

1.8-V

Controller

3.3-V

System

SN74AVC(H)24T245

1B1/1B2/1B3/1B4

1A1/1A2/1A3/1A4

2A1/2A2/2A3/2A4

3A1/3A2/3A3/3A4

4A1/4A2/4A3/4A4

5A1/5A2/5A3/5A4

6A1/6A2/6A3/6A4

2B1/2B2/2B3/2B4

3B1/3B2/3B3/3B4

4B1/4B2/4B3/4B4

5B1/5B2/5B3/5B4

Data

6B1/6B2/6B3/6B4

GND

Figure 9-1. Application Schematic

9.3.1 Design Requirements

This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the

intended flow of data and take care not to violate any of the high or low logic levels. Unused data inputs must not

be floating, as this can cause excessive internal leakage on the input CMOS structure. Tie any unused input and

output ports directly to ground.

For this design example, use the parameters listed in the Electrical Characteristics.

Table 9-1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Input voltage range

1.2 V to 3.6 V

Output voltage range

1.2 V to 3.6 V

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9.3.2 Detailed Design Procedure

To begin the design process, determine the following:

9.3.2.1 Input Voltage Ranges

Use the supply voltage of the device that is driving the SN74AVC24T245 device to determine the input voltage

range. For a valid logic high the value must exceed the V_IHof the input port. For a valid logic low the value must

be less than the V_ILof the input port.

9.3.2.2 Output Voltage Range

Use the supply voltage of the device that the SN74AVC24T245 device is driving to determine the output voltage

range.

9.3.3 Application Curve

Input (1.2 V)

Output (3.3 V)

Figure 9-2. Translation Up (1.2 V to 3.3 V) at 2.5 MHz

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10 Power Supply Recommendations

The SN74AVC24T245 device uses two separate configurable power-supply rails, V_CCAand V_CCB. VCCA accepts

any supply voltage from 1.2 V to 3.6 V and V_CCBaccepts any supply voltage from 1.2 V to 3.6 V. The A port and

B port are designed to track V_CCAand V_CCB, respectively, allowing for low-voltage bidirectional translation

between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V and 3.3-V voltage nodes.

The output-enable OE input circuit is designed so that it is supplied by V_CCAand when the OE input is high, all

outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power

up or power down, the OE input pin must be tied to V_CCAthrough a pullup resistor and must not be enabled until

V_CCAand V_CCBare fully ramped and stable. The minimum value of the pullup resistor to V_CCAis determined by

the current-sinking capability of the driver.

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit-board layout guidelines is recommended.

•

Bypass capacitors must be used on power supplies.

Short trace lengths must be used to avoid excessive loading.

Place pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of

signals, depending on the system requirements.

11.2 Layout Example

0.8mm

pitch

0.50mm dia.

solder mask

opening

0.350mm

Dia. Pad

0.254mm

dia. hole

0.125mm

Trace

Figure 11-1. BGA Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.2 Related Documentation

For related documentation, see the following:

http://www.ti.com/lit/an/scea014/scea014.pdf

12.3 Trademarks

All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.5 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

29-Aug-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74AVC24T245GRGR BGA MI

GRG

83

1000

330.0

24.4

4.8

10.3

1.8

8.0

24.0

Q1

CROSTA

R JUNI

OR

SN74AVC24T245ZRGR BGA MI

ZRG

83

1000

330.0

24.4

4.8

10.3

1.8

8.0

24.0

Q1

CROSTA

R JUNI

OR

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Aug-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74AVC24T245GRGR BGA MICROSTAR

JUNIOR

GRG

83

1000

350.0

43.0

SN74AVC24T245ZRGR BGA MICROSTAR

JUNIOR

ZRG

83

1000

350.0

43.0

Pack Materials-Page 2

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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型号：	SN74AVC24T245NMUR
厂家：	TEXAS INSTRUMENTS
描述：	24-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation And 3-State Outputs
文件：	总29页 (文件大小：1768K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74AVC24T245NMUR [TI]

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