SN74AVC2T45_15 [TI]
2-Supply, Bus Transceiver;
| 型号： | SN74AVC2T45_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2-Supply, Bus Transceiver |
| 文件： | 总21页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
FEATURES
•
Max Data Rates
•
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
– 500 Mbps (1.8-V to 3.3-V Translation)
– 320 Mbps (<1.8-V to 3.3-V Translation)
– 320 Mbps (Translate to 2.5 V or 1.8 V)
– 180 Mbps (Translate to 1.5 V)
Control Inputs VIH/VIL Levels Are Referenced
to VCCA Voltage
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
– 240 Mbps (Translate to 1.2 V)
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
•
I/Os Are 4.6-V Tolerant
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Ioff Supports Partial-Power-Down Mode
Operation
BBBB
BBBB
BBBB
– 1000-V Charged-Device Model (C101)
DCT OR DCU PACKAGE
(TOP VIEW)
YEP OR YZP PACKAGE
(BOTTOM VIEW)
4
3
2
1
5
6
7
8
V
V
CCB
1
2
3
4
8
7
6
5
GND
A2
DIR
B2
CCA
A1
A2
B1
B2
DIR
A1
B1
GND
V
CCA
V
CCB
DESCRIPTION/ORDERING INFORMATION
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track
VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional
translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVC2T45 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input.
The SN74AVC2T45 is designed so that the DIR input is powered by VCCA
.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
SN74AVC2T45YEPR
_ _ _TD_
Tape and reel
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SN74AVC2T45YZPR
–40°C to 85°C
SSOP – DCT
Tape and reel
Tape and reel
SN74AVC2T45DCTR
SN74AVC2T45DCUR
DT2_ _ _
DT2_
VSSOP – DCU
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
FUNCTION TABLE
(EACH TRANSCEIVER)
INPUT
OPERATION
DIR
L
B data to A bus
A data to B bus
H
LOGIC DIAGRAM (POSITIVE LOGIC)
5
2
DIR
A1
7
6
B1
B2
3
A2
V
CCA
V
CCB
2
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCA
Supply voltage range
VCCB
–0.5
4.6
V
I/O ports (A port)
I/O ports (B port)
Control inputs
A port
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
4.6
4.6
VI
Input voltage range(2)
V
4.6
4.6
Voltage range applied to any output in the high-impedance or
power-off state(2)
VO
VO
V
V
B port
4.6
A port
VCCA + 0.5
VCCB + 0.5
–50
Voltage range applied to any output in the high or low state(2)(3)
B port
IIK
IOK
IO
Input clamp current
VI < 0
mA
mA
mA
mA
Output clamp current
VO < 0
–50
Continuous output current
±50
Continuous current through VCCA, VCCB, or GND
±100
220
DCT package
θJA
Package thermal impedance(4)
DCU package
227
°C/W
°C
YEP/YZP package
102
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current ratings are observed.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
Recommended Operating Conditions(1)(2)(3)(4)(5)
VCCI
VCCO
MIN
MAX
3.6
UNIT
VCCA
VCCB
Supply voltage
Supply voltage
1.2
V
1.2
3.6
V
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
VCCI × 0.65
High-level
input voltage
VIH
VIL
VIH
VIL
Data inputs(4)
Data inputs(4)
1.6
2
V
VCCI × 0.35
Low-level
input voltage
0.7
0.8
V
V
V
VCCA × 0.65
High-level
input voltage
DIR
1.6
2
(5)
(5)
(referenced to VCCA
)
)
VCCA × 0.35
Low-level
input voltage
DIR
0.7
0.8
3.6
VCCO
3.6
–3
–6
–8
–9
–12
3
(referenced to VCCA
VI
Input voltage
0
0
0
V
V
Active state
3-state
VO
Output voltage
1.2 V
1.4 V to 1.6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
1.2 V
IOH
High-level output current
Low-level output current
mA
mA
1.4 V to 1.6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
6
IOL
8
9
12
5
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
TA
–40
85
°C
(1) VCCI is the VCC associated with the data input port.
(2) VCCO is the VCC associated with the output port.
(3) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(4) For VCCI values not specified in the data sheet, VIH(min) = VCCI x 0.7 V, VIL(max) = VCCI x 0.3 V.
(5) For VCCI values not specified in the data sheet, VIH(min) = VCCA x 0.7 V, VIL(max) = VCCA x 0.3 V.
4
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
Electrical Characteristics(1)(2)
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
–40°C to 85°C
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VCCA
VCCB
UNIT
MIN
TYP
MAX
MIN
MAX
VCCO
– 0.2 V
1.2 V to 3.6 V
1.2 V to 3.6 V
IOH = –3 mA
IOH = –6 mA
IOH = –8 mA
IOH = –9 mA
IOH = –12 mA
IOL = 100 µA
IOL = 3 mA
1.2 V
1.4 V
1.2 V
1.4 V
0.95
0.25
1.05
1.2
VOH
VI = VIH
V
1.65 V
2.3 V
1.65 V
2.3 V
1.75
2.3
3 V
3 V
1.2 V to 3.6 V
1.2 V
1.2 V to 3.6 V
1.2 V
0.2
IOL = 6 mA
1.4 V
1.4 V
0.35
0.45
0.55
0.7
VOL
VI = VIL
V
IOL = 8 mA
1.65 V
2.3 V
1.65 V
2.3 V
IOL = 9 mA
IOL = 12 mA
3 V
3 V
DIR
input
II
VI = VCCA or GND
1.2 V to 3.6 V
1.2 V to 3.6 V
±0.025 ±0.25
±1
µA
µA
µA
A port
Ioff
0 V
0 to 3.6 V
0 V
±0.1
±0.1
±1
±1
±5
±5
VI or VO = 0 to 3.6 V
VO = VCCO or GND
B port
0 to 3.6 V
A or B
IOZ
1.2 V to 3.6 V
1.2 V to 3.6 V
±0.5
±2.5
±5
ports
1.2 V to 3.6 V
0 V
1.2 V to 3.6 V
3.6 V
10
–2
10
10
10
–2
VI = VCCI or
GND,
ICCA
IO = 0
µA
µA
3.6 V
0 V
1.2 V to 3.6 V
0 V
1.2 V to 3.6 V
3.6 V
VI = VCCI or
GND,
ICCB
IO = 0
IO = 0
3.6 V
0 V
VI = VCCI or
GND,
ICCA + ICCB
1.2 V to 3.6 V
3.3 V
1.2 V to 3.6 V
3.3 V
20
µA
pF
pF
Control
inputs
Ci
VI = 3.3 V or GND
VO = 3.3 V or GND
2.5
6
A or B
Cio
3.3 V
3.3 V
ports
(1) VCCO is the VCC associated with the output port.
(2) VCCI is the VCC associated with the input port.
5
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 11)
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
TYP
3.1
3.1
3.4
3.4
5.2
5.2
5
TYP
2.6
2.6
3.1
3.1
5.2
5.2
4
TYP
2.4
2.4
3
TYP
2.2
2.2
2.9
2.9
5
TYP
2.2
2.2
2.9
2.9
4.8
4.8
3.2
3.2
6.1
6.1
7
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
A
B
A
A
B
A
B
B
ns
3
5.1
5.1
3.8
3.8
6.8
6.8
7.5
7.5
DIR
DIR
DIR
DIR
ns
5
2.8
2.8
5.7
5.7
7.2
7.2
ns
5
4
(1)
tPZH
8.4
8.4
8.3
8.3
7.1
7.1
7.8
7.8
ns
(1)
tPZL
(1)
tPZH
ns
(1)
tPZL
7
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 11)
VCCB = 1.5 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
± 0.1 V
± 0.2 V
± 0.3 V
PARAMETER
UNIT
TYP
2.8
2.8
2.7
2.7
3.9
3.9
4.7
4.7
7.4
7.4
6.7
6.7
MIN
0.7
0.7
0.8
0.8
1.3
1.3
1.1
1.1
MAX
5.4
5.4
5.4
5.4
8.5
8.5
7
MIN
0.5
0.5
0.7
0.7
1.3
1.3
1.4
1.4
MAX
4.6
MIN
0.4
0.4
0.6
0.6
1.1
1.1
1.2
1.2
MAX
3.7
MIN
0.3
0.3
0.5
0.5
1.4
1.4
1.7
1.7
MAX
3.5
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
4.6
3.7
3.5
5.2
4.9
4.7
B
5.2
4.9
4.7
7.8
7.7
7.6
DIR
DIR
DIR
DIR
7.8
7.7
7.6
6.9
6.9
7.1
7
6.9
6.9
7.1
(1)
tPZH
12.4
12.4
13.9
13.9
12.1
12.1
11.6
11.6
11.8
11.8
9.1
11.8
11.8
7.8
(1)
tPZL
(1)
tPZH
(1)
tPZL
9.1
7.8
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
6
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 11)
VCCB = 1.5 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
± 0.1 V
± 0.2 V
± 0.3 V
PARAMETER
UNIT
TYP
2.7
2.7
2.4
2.4
3.7
3.7
4.4
4.4
6.8
6.8
6.4
6.4
MIN
0.5
0.5
0.7
0.7
1.3
1.3
1.3
1.3
MAX
5.2
MIN
0.4
0.4
0.5
0.5
0.7
0.7
1.3
1.3
MAX
4.3
MIN
0.2
0.2
0.5
0.5
1.4
1.4
0.8
0.8
MAX
3.4
3.4
4
MIN
0.2
0.2
0.4
0.4
1.1
1.1
1.5
1.5
MAX
3.1
3.1
3.8
3.8
4.5
4.5
5.9
5.9
9.7
9.7
7.4
7.4
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
5.2
4.3
4.7
4.4
B
4.7
4.4
4
8.1
6.9
5.3
5.3
5.7
5.7
9.7
9.7
8.6
8.6
DIR
DIR
DIR
DIR
8.1
6.9
5.8
5.9
5.8
5.9
(1)
tPZH
10.4
10.4
13.3
13.3
10.3
10.3
11.2
11.2
(1)
tPZL
(1)
tPZH
(1)
tPZL
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 11)
VCCB = 1.5 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
± 0.1 V
± 0.2 V
± 0.3 V
PARAMETER
UNIT
TYP
2.6
2.6
2.1
2.1
2.4
2.4
3.8
3.8
5.9
5.9
5
MIN
0.4
0.4
0.6
0.6
0.7
0.7
1
MAX
4.9
MIN
0.2
0.2
0.5
0.5
0.8
0.8
0.6
0.6
MAX
4
MIN
0.2
0.2
0.4
0.4
0.8
0.8
0.5
0.5
MAX
3
MIN
0.2
0.2
0.3
0.3
0.5
0.5
1.1
1.1
MAX
2.6
2.6
2.8
2.8
4.3
4.3
4.1
4.1
6.9
6.9
6.8
6.8
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
4.9
4
3
3.8
3.4
3.4
6.4
6.4
4.3
4.3
7.7
7.7
10.4
10.4
3
B
3.8
3
7.9
5
DIR
DIR
DIR
DIR
7.9
5
4.3
4.2
4.2
7.2
7.2
7.9
7.9
1
4.3
(1)
tPZH
7.9
(1)
tPZL
7.9
(1)
tPZH
12.8
12.8
(1)
tPZL
5
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
7
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 11)
VCCB = 1.5 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
VCCB = 3.3 V
± 0.3 V
VCCB = 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
± 0.1 V
± 0.2 V
PARAMETER
UNIT
TYP
2.5
2.5
2.1
2.1
2.9
2.9
3.4
3.4
5.5
5.5
5.4
5.4
MIN
0.3
0.3
0.6
0.6
1.1
1.1
0.5
0.5
MAX
4.7
4.7
3.6
3.6
8
MIN
0.2
0.2
0.4
0.4
1
MAX
3.8
MIN
0.2
0.2
0.3
0.3
1.3
1.3
0.3
0.3
MAX
2.8
2.8
2.6
2.6
4.7
4.7
4.6
4.6
6.2
6.2
7.4
7.4
MIN MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
0.2
0.2
0.3
0.3
1.2
1.2
1.1
1.1
2.4
2.4
2.4
2.4
4
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
3.8
3.1
B
3.1
6.5
DIR
DIR
DIR
DIR
8
1
6.5
4
6.6
6.6
6.9
6.9
12.7
12.7
0.3
0.3
5.6
3.5
3.5
5.9
5.9
6.3
6.3
5.6
(1)
tPZH
6.6
(1)
tPZL
6.6
(1)
tPZH
10.3
10.3
(1)
tPZL
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
Operating Characteristics
TA = 25°C
VCCA
=
VCCA
=
VCCA
=
VCCA
=
VCCA =
TEST
CONDITIONS
VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V
PARAMETER
UNIT
TYP
TYP
TYP
TYP
TYP
A-port input,
B-port output
3
3
3
3
4
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
(1)
(1)
CpdA
pF
B-port input,
A-port output
12
12
3
13
13
3
13
13
3
14
14
3
15
15
4
A-port input,
B-port output
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
CpdB
pF
B-port input,
A-port output
(1) Power-dissipation capacitance per transceiver
8
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
Power-Up Considerations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up VCCA
.
3. VCCB can be ramped up along with or after VCCA
.
Table 1. Typical Total Static Power Consumption (ICCA + ICCB
)
VCCA
VCCB
UNIT
0 V
0
1.2 V
<0.5
<1
1.5 V
<0.5
<1
1.8 V
<0.5
<1
2.5 V
<0.5
<1
3.3 V
<0.5
1
0 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
<0.5
<0.5
<0.5
<0.5
<0.5
<1
<1
<1
<1
1
µA
<1
<1
<1
<1
<1
1
<1
<1
<1
<1
1
<1
<1
<1
<1
9
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE, TA = 25°C, VCCA = 1.2 V
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
V
= 1.2 V
= 1.5 V
= 1.8 V
V
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
CCB
CCB
CCB
V
V
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C - pF
L
C - pF
L
Figure 1.
Figure 2.
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE, TA = 25°C, VCCA = 1.5 V
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
= 1.2 V
= 1.5 V
= 1.8 V
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
CCB
V
V
V
V
CCB
CCB
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C - pF
L
C - pF
L
Figure 3.
Figure 4.
10
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE, TA = 25°C, VCCA = 1.8 V
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
V
= 1.2 V
= 1.5 V
= 1.8 V
V
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
CCB
CCB
CCB
V
V
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
L
- pF
C - pF
L
Figure 5.
Figure 6.
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE, TA = 25°C, VCCA = 2.5 V
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
= 1.2 V
= 1.5 V
= 1.8 V
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
CCB
V
V
V
V
CCB
CCB
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
L
- pF
C - pF
L
Figure 7.
Figure 8.
11
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE, TA = 25°C, VCCA = 3.3 V
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
V
= 1.2 V
= 1.5 V
= 1.8 V
V
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
CCB
CCB
CCB
V
V
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
L
- pF
C - pF
L
Figure 9.
Figure 10.
12
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
2 × V
CCO
TEST
S1
S1
R
L
Open
GND
t
Open
pd
From Output
Under Test
t
t
/t
/t
2 × V
CCO
GND
PLZ PZL
PHZ PZH
C
L
R
L
(see Note A)
t
w
LOAD CIRCUIT
V
CCI
V
CCI
/2
V
CCI
/2
Input
C
L
V
TP
R
L
V
CCO
0 V
1.2 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
15 pF
15 pF
15 pF
15 pF
15 pF
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
V
CCA
Output
Control
(low-level
enabling)
V /2
CCA
V
CCA
/2
t
0 V
t
PZL
PLZ
V
V
CCO
Output
Waveform 1
V
CCI
V
/2
/2
CCO
Input
V
CCI
/2
V
CCI
/2
V
+ V
OL
TP
S1 at 2 × V
CCO
OL
0 V
(see Note B)
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
- V
TP
V
CCO
Output
V /2
CCO
V
CCO
/2
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
H.
I.
t
t
t
V
V
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
pd
PHL
is the V associated with the input port.
CC
CCI
is the V associated with the output port.
CCO
CC
Figure 11. Load Circuit and Voltage Waveforms
13
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
APPLICATION INFORMATION
Figure 12 is an example circuit of the SN74AVC2T45 used in a bidirectional logic level-shifting application.
V
CC1
V
CC2
V
CC1
V
CC2
1
2
3
4
8
7
6
5
V
CC2
V
CC1
SYSTEM-1
SYSTEM-2
DESCRIPTION
PIN
1
NAME
VCCA
A1
FUNCTION
VCC1
SYSTEM-1 supply voltage (1.2 V to 3.6 V)
Output level depends on VCC1 voltage.
Output level depends on VCC1 voltage.
Device GND
2
OUT1
OUT2
GND
DIR
3
A2
4
GND
DIR
B2
5
The GND (low-level) determines B-port to A-port direction.
Input threshold value depends on VCC2 voltage.
Input threshold value depends on VCC2 voltage.
SYSTEM-2 supply voltage (1.2 V to 3.6 V)
6
IN2
7
B1
IN1
8
VCCB
VCC2
Figure 12. Bidirectional Logic Level-Shifting Application
14
SN74AVC2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES531F–DECEMBER 2003–REVISED MAY 2005
APPLICATION INFORMATION
Figure 13 shows the SN74AVC2T45 used in a bidirectional logic level-shifting application. Since the
SN74AVC2T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
V
CC1
V
CC1
V
CC2
V
CC2
Pullup/Pulldown
Pullup/Pulldown
(1)
I/O-1
I/O-2
(1)
or Bus Hold
or Bus Hold
1
2
3
4
8
7
6
5
DIR CTRL
SYSTEM-1
SYSTEM-2
Following is a sequence that illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from
SYSTEM-2 to SYSTEM-1.
STATE
DIR CTRL
I/O-1
I/O-2
DESCRIPTION
1
H
Out
In
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are
disabled.
2
H
Hi-Z
Hi-Z
The bus-line state depends on pullup or pulldown.(1)
DIR bit is flipped. I/O-1 and I/O-2 still are disabled.
The bus-line state depends on pullup or pulldown.(1)
3
4
L
L
Hi-Z
Out
Hi-Z
In
SYSTEM-2 data to SYSTEM-1
(1) SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 13. Bidirectional Logic Level-Shifting Application
Enable Times
Calculate the enable times for the SN74AVC2T45 using the following formulas:
•
•
•
•
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVC2T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
15
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
SN74AVC2T45DCTR
SN74AVC2T45DCTRE4
SN74AVC2T45DCTT
SN74AVC2T45DCUR
SN74AVC2T45DCURE4
SN74AVC2T45DCUT
SN74AVC2T45DCUTE4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SM8
DCT
8
8
8
8
8
8
8
3000
3000
250
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
SM8
SM8
US8
US8
US8
US8
DCT
DCT
DCU
DCU
DCU
DCU
Pb-Free
(RoHS)
Pb-Free
(RoHS)
3000
3000
250
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
250
Pb-Free
(RoHS)
SN74AVC2T45YEPR
SN74AVC2T45YZPR
ACTIVE
ACTIVE
WCSP
WCSP
YEP
YZP
8
8
3000
3000
TBD
SNPB
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Pb-Free
(RoHS)
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,13
0,65
8
5
0,15 NOM
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
0,25
1
4
0° – 8°
0,60
0,20
3,15
2,75
1,30 MAX
Seating Plane
0,10
0,10
0,00
4188781/C 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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