SN74AXC4T245QPWRQ1 [TI]

具有可配置电压转换和三态输出的汽车类 4 位双电源总线收发器 | PW | 16 | -40 to 125;


型号：	SN74AXC4T245QPWRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有可配置电压转换和三态输出的汽车类 4 位双电源总线收发器 \| PW \| 16 \| -40 to 125 总线收发器
文件：	总44页 (文件大小：2834K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74AXC4T245-Q1

ZHCSK08E –JULY 2019 –REVISED DECEMBER 2021

具有可配置电压转换和三态输出的SN74AXC4T245-Q1 汽车4 位双电源总线收

发器

SN74AXC4T245-Q1 器件旨在实现数据总线之间的异

步通信。根据方向控制输入（DIR1 和 2DIR）的逻辑

1 特性

• 符合面向汽车应用的AEC-Q100 标准

• 采用可湿侧面QFN (WBQB) 封装

• 完全可配置的双轨设计可允许各个端口在0.65V 至

3.6V 的电源电压范围内运行

• 工作温度范围为–40°C 至+125°C

• 多向控制引脚，支持同步升降转换

• 无干扰电源定序

• 从1.8V 转换到3.3V 时，支持高达380Mbps 的转

换速率

• V_CC隔离特性：

电平，此器件将数据从 A 总线传输至 B 总线，或者将

数据从B 总线传输至A 总线。输出使能输入（1 OE 和

2 OE ）可用于禁用输出，从而有效隔离总线。

SN74AXC4T245-Q1 器件旨在使控制引脚（xDIR 和 x

OE）以V_CCA为基准。

为了确保电平转换器I/O 在加电或断电期间处于高阻抗

状态，x OE 引脚应通过一个上拉电阻器连接至V_CCA。

该器件完全适合使用 I_off电流的局部断电应用。当器件

断电时，I_off保护电路可确保不从输入、输出或偏置到

特定电压的组合 I/O 获取多余电流，也不向其提供多余

电流。

– 如果任何一个V_CC输入低于100mV，则所有

I/O 输出均禁用且处于高阻抗状态

• I_off支持局部断电模式运行

• 兼容AVC 系列电平转换器

• 闩锁性能超过100mA，符合JESD 78 II 类规范

• ESD 保护性能超过JEDEC JS-001 规范要求

V_CC隔离特性可确保当 V_CCA或 V_CCB低于 100mV

时，I/O 端口均禁用其输出并进入高阻态。

无干扰电源定序使电源轨能以任何顺序打开或关断，从

而提供强大的电源定序性能。

– 8000V 人体放电模型

– 1000V 充电器件模型

器件信息

封装⁽¹⁾

TSSOP (16)

WQFN (16)

封装尺寸（标称值）

5.00mm × 4.40mm

2.50mm × 3.50mm

2.60mm x 1.80mm

器件型号

2 应用

SN74AXC4T245PW-Q1

SN74AXC4T245BQB-Q1

• 信息娱乐系统音响主机

• ADAS 融合

• ADAS 前置摄像头

• 混合动力电动汽车和电动汽车电池管理系统

• 远程信息处理控制单元

SN74AXC4T245WBQB-Q1 WQFN (16)

SN74AXC4T245RSV-Q1 UQFN (16)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

3 说明

One of Two Transceiver Pairs

符合AEC-Q100 标准的SN74AXC4T245-Q1 器件是一

款采用两个独立可配置电源轨的四位同相总线收发器。

V_CCA

V_CCB

xDIR

xOE

_CCA和 V_CCB电源电压低至 0.65V 时，该器件可正常

工作。A 端口用于跟踪 V_CCA，该端口可支持 0.65V 至

3.6V 范围内的任何电源电压。B 端口用于跟踪 V_CCB

xB1

xB2

xA1

xA2

，

该端口也可支持 0.65V 至 3.6V 范围内的任何电源电

压。此外，SN74AXC4T245-Q1 还与单电源系统兼

容。

功能方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCES905

SN74AXC4T245-Q1

ZHCSK08E –JULY 2019 –REVISED DECEMBER 2021

www.ti.com.cn

Table of Contents

7.1 Load Circuit and Voltage Waveforms........................18

8 Detailed Description......................................................20

8.1 Overview...................................................................20

8.2 Functional Block Diagram.........................................20

8.3 Feature Description...................................................20

8.4 Device Functional Modes..........................................22

9 Application and Implementation..................................23

9.1 Application Information............................................. 23

9.2 Typical Application.................................................... 23

10 Power Supply Recommendations..............................25

11 Layout...........................................................................25

11.1 Layout Guidelines................................................... 25

11.2 Layout Example...................................................... 25

12 Device and Documentation Support..........................26

12.1 Documentation Support.......................................... 26

12.2 接收文档更新通知................................................... 26

12.3 支持资源..................................................................26

12.4 Trademarks.............................................................26

12.5 Electrostatic Discharge Caution..............................26

12.6 术语表..................................................................... 26

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Switching Characteristics, V_CCA= 0.7 V ± 0.05 V.......7

6.7 Switching Characteristics, V_CCA= 0.8 V ± 0.04 V.......8

6.8 Switching Characteristics, V_CCA= 0.9 V ± 0.045 V.....9

6.9 Switching Characteristics, V_CCA= 1.2 V ± 0.1 V.......10

6.10 Switching Characteristics, V_CCA= 1.5 V ± 0.1 V..... 11

6.11 Switching Characteristics, V_CCA= 1.8 V ± 0.15 V... 12

6.12 Switching Characteristics, V_CCA= 2.5 V ± 0.2 V.....13

6.13 Switching Characteristics, V_CCA= 3.3 V ± 0.3 V.....14

6.14 Operating Characteristics: T_A= 25°C..................... 15

6.15 Typical Characteristics............................................17

7 Parameter Measurement Information..........................18

Information.................................................................... 26

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision D (September 2021) to Revision E (December 2021)

Page

• 将WBQB 封装的状态从：产品预发布更改为“量产”.....................................................................................1

Changes from Revision C (March 2021) to Revision D (September 2021)

Page

• 为APL 添加了BQB (WQFN) 封装..................................................................................................................... 1

Changes from Revision B (July 2020) to Revision C (March 2021)

Page

• 将BQB (WQFN) 封装选项的状态从预发布更改为量产.....................................................................................1

Changes from Revision A (December 2019) to Revision B (July 2020)

Page

• 更新了整个文档中的表、图和交叉参考的编号格式.............................................................................................1

• 向器件信息表添加了BQB (WQFN) 封装选项....................................................................................................1

Changes from Revision * (July 2019) to Revision A (December 2019)

Page

• 将“预告信息”更改为“量产数据”.................................................................................................................. 1

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5 Pin Configuration and Functions

V_CCA

1DIR

2DIR

1A1

V_CCB

1OE

2OE

1B1

1B2

2B1

2B2

GND

1DIR

2DIR

1A1

1A2

2A1

2A2

1OE

2OE

13 1B1

12 1B2

11 2B1

10 2B2

Thermal

Pad

1A2

2A1

2A2

GND

图5-1. PW Package 16-Pin TSSOP Top View

图5-2. BQB/WBQB Package 16-Pin WQFN

Transparent Top View

16 15 14 13

2B2

GND

2A2

1OE

V_CCB

V_CCA

1DIR

图5-3. RSV Package 16-Pin UQFN Transparent Top View

表5-1. Pin Functions

NAME

NO.

TYPE

DESCRIPTION

RSV

BQB

1A1

1A2

1B1

1B2

1DIR

I/O

Input/output 1A1. Referenced to V_CCA

Input/output 1A2. Referenced to V_CCA

Input/output 1B1. Referenced to V_CCB

Input/output 1B2. Referenced to V_CCB

Direction-control input for ‘1’ports. Referenced to V_CCA

Tri-state output-mode enable. Pull OE high to place ‘1’outputs in

tri-state mode. Referenced to V_CCA

1 OE

2A1

2A2

2B1

2B2

2DIR

I/O

Input/output 2A1. Referenced to V_CCA

Input/output 2A2. Referenced to V_CCA

Input/output 2B1. Referenced to V_CCB

Input/output 2B2. Referenced to V_CCB

Direction-control input for ‘2’ports. Referenced to V_CCA

Tri-state output-mode enable. Pull OE high to place ‘2’outputs in

tri-state mode. Referenced to V_CCA

2 OE

GND

V_CCA

V_CCB

8, 9

10, 11

8, 9

Ground

—

A-port power supply voltage. 0.65 V ≤V_CCA≤3.6 V

B-port power supply voltage. 0.65 V ≤V_CCB≤3.6 V

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

–50

MAX UNIT

V_CCASupply voltage A

V_CCBSupply voltage B

4.2

I/O Ports (A Port)

I/O Ports (B Port)

Control Inputs

A Port

4.2

V_I

Input Voltage⁽²⁾

4.2

V_O

Voltage applied to any output in the high-impedance or power-off state⁽²⁾

Voltage applied to any output in the high or low state^{(2) (3)}

B Port

4.2

A Port

V_CCA+ 0.2

V_CCB+ 0.2

B Port

I_IK

I_OK

I_O

Input clamp current

V_I< 0

Output clamp current

V_O< 0

–50

Continuous output current

Continuous current through V_CCor GND

Junction Temperature

50 mA

100 mA

150 °C

–50

–100

T_j

T_stg

Storage temperature

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.

6.2 ESD Ratings

VALUE

±8000

±1000

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Charged device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

0.65

MAX UNIT

V_CCA

V_CCB

Supply voltage A

Supply voltage B

3.6

0.65

V_CCI= 0.65 V - 0.75 V

V_CCI= 0.76 V - 1 V

V_CCI= 1.1 V - 1.95 V

V_CCI= 2.3 V - 2.7 V

V_CCI= 3 V - 3.6 V

V_CCIx 0.70

V_CCIx 0.65

1.6

Data Inputs

V_IH

High-level input voltage

V_CCA= 0.65 V - 0.75 V

V_CCA= 0.76 V - 1 V

V_CCA= 1.1 V - 1.95 V

V_CCA= 2.3 V - 2.7 V

V_CCA= 3 V - 3.6 V

V_CCI= 0.65 V - 0.75 V

V_CCI= 0.76 V - 1 V

V_CCI= 1.1 V - 1.95 V

V_CCI= 2.3 V - 2.7 V

V_CCI= 3 V - 3.6 V

V_CCAx 0.70

V_CCAx 0.65

1.6

Control Inputs(xDIR, x OE)

Referenced to V_CCA

V_CCIx 0.30

V_CCIx 0.35

0.7

Data Inputs

0.8

V_IL

Low-level input voltage

V_CCA= 0.65 V - 0.75 V

V_CCA= 0.76 V - 1 V

V_CCA= 1.1 V - 1.95 V

V_CCA= 2.3 V - 2.7 V

V_CCA= 3 V - 3.6 V

V_CCAx 0.30

V_CCAx 0.35

0.7

Control Inputs(xDIR, x OE)

Referenced to V_CCA

0.8

V_I

Input voltage ⁽²⁾

Output voltage

3.6

Active State

Tri-State

V_CCO

V_O

3.6

Δt/

Input transition rate

10 ns/V

125 °C

Δv⁽²⁾

T_A

Operating free-air temperature

–40

(1) V_CCIis the V_CCassociated with the input port. V_CCOis the V_CCassociated with the output port.

(2) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs.

6.4 Thermal Information

SN74AXC4T245-Q1

BQB

(WQFN)

WBQB

(WQFN)

THERMAL METRIC⁽¹⁾

PW (TSSOP) RSV (UQFN)

UNIT

16 PINS

126.9

49.3

74.3

8.1

16 PINS

130.1

70.3

57.4

4.6

16 PINS

73.0

35.1

42.8

4.6

16 PINS

72.9

69.6

41.9

4.6

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JT

73.4

55.8

42.8

10.2

41.9

19.9

ψ_JB

R_θJC(bottom)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) ^{(1) (2)}

Operating free-air temperature (T_A)

PARAMETER

TEST CONDITIONS

V_CCA

V_CCB

UNIT

–40°C to 85°C

–40°C to 125°C

MIN TYP⁽⁴⁾

MAX

MIN TYP⁽⁴⁾

MAX

V_CCO

–0.1

V_CCO

–0.1

0.7 V - 3.6 V

I_OH= –100 µA

0.65 V

0.76 V

0.85 V

1.1 V

0.65 V

0.76 V

0.85 V

1.1 V

0.55

0.58

0.65

0.85

1.05

1.2

0.55

0.58

0.65

0.85

1.05

1.2

I_OH= –50 µA

I_OH= –200 µA

I_OH= –500 µA

High-level output

voltage

V_OH

V_I= V_IH

I_OH= –3 mA

I_OH= –6 mA

I_OH= –8 mA

I_OH= –9 mA

I_OH= –12 mA

I_OL= 100 µA

I_OL= 50 µA

I_OL= 200 µA

I_OL= 500 µA

I_OL= 3 mA

1.4 V

1.65 V

2.3 V

1.65 V

2.3 V

1.75

2.3

1.75

2.3

3 V

0.7 V - 3.6 V

0.65 V

0.76 V

0.85 V

1.1 V

0.7 V - 3.6 V

0.65 V

0.76 V

0.85 V

1.1 V

0.1

0.18

0.2

0.18

0.2

Low-level output

voltage

V_OL

V_I= V_IL

0.25

0.35

0.45

0.55

0.7

0.25

0.35

0.45

0.55

0.7

I_OL= 6 mA

1.4 V

I_OL= 8 mA

1.65 V

2.3 V

1.65 V

2.3 V

I_OL= 9 mA

I_OL= 12 mA

3 V

Control inputs (xDIR, x OE): V_I

= V_CCAor GND

0.65 V- 3.6 V

0.5

µA

–0.5

–4

–1

–8

Input leakage

current

I_I

Data Inputs (xAx, xBx)

V_I= V_CCIor GND

0 V

0 V - 3.6 V

0 V

–4

–8

Partial power

down current

A or B Port

V_Ior V_O= 0 V - 3.6 V

I_off

µA

0 V - 3.6 V

A or B Port

Tri-state output

current ⁽³⁾

I_OZ

V_I= V_CCIor GND, V_O= V_CCO3.6 V

or GND, OE = V_IH

3.6 V

–4

–2

–8

0.65 V- 3.6 V

3.6 V

V_CCAsupply

current

V_I= V_CCI

or GND

I_CCA

I_O= 0

0 V

µA

–12

3.6 V

0 V

0.65 V- 3.6 V

0 V

0.65 V- 3.6 V

3.6 V

V_CCBsupply

current

V_I= V_CCI

or GND

I_CCB

I_O= 0

3.6 V

0 V

–2

–12

I_CCA

I_CCB

Combined

supply current

V_I= V_CCI

or GND

0.65 V- 3.6 V

3.3 V

0.65 V- 3.6 V

3.3 V

µA

Control input

capacitance

C_i

V_I= 3.3 V or GND

4.5

6.6

4.5

6.6

Data I/O

capacitance

OE = V_CCA, V_O= 1.65V DC +1

MHz -16 dBm sine wave

C_io

3.3 V

(1) V_CCIis the V_CCassociated with the input port.

(2) V_CCOis the V_CCassociated with the output port.

(3) For I/O ports, the parameter I_OZincludes the input leakage current.

(4) All typical data is taken at 25°C.

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6.6 Switching Characteristics, V_CCA= 0.7 V ± 0.05 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

0.5

155

156

154

238

286

0.5

108

128

156

121

238

194

0.5

185

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

Propagation

delay

t_pd

106

156

101

238

146

156

125

238

146

t_disDisable time

238

t_enEnable time

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6.7 Switching Characteristics, V_CCA= 0.8 V ± 0.04 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

0.5

128

108

103

143

243

0.5

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

Propagation

delay

t_pd

103

110

143

172

103

t_disDisable time

143

129

143

t_enEnable time

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6.8 Switching Characteristics, V_CCA= 0.9 V ± 0.045 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

0.5

106

0.5

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

Propagation

delay

t_pd

t_disDisable time

138

105

t_enEnable time

222

148

116

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6.9 Switching Characteristics, V_CCA= 1.2 V ± 0.1 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

0.5

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

Propagation

delay

t_pd

t_disDisable time

132

t_enEnable time

164

108

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6.10 Switching Characteristics, V_CCA= 1.5 V ± 0.1 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

0.5

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

Propagation

delay

t_pd

t_disDisable time

131

t_enEnable time

109

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6.11 Switching Characteristics, V_CCA= 1.8 V ± 0.15 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

0.5

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

Propagation

delay

t_pd

t_disDisable time

130

t_enEnable time

102

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6.12 Switching Characteristics, V_CCA= 2.5 V ± 0.2 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

0.5

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

Propagation

delay

t_pd

t_disDisable time

128

t_enEnable time

120

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6.13 Switching Characteristics, V_CCA= 3.3 V ± 0.3 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

)

PARAMETER

FROM

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

0.5

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

Propagation

delay

t_pd

185

t_disDisable time

141

t_enEnable time

189

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6.14 Operating Characteristics: T_A= 25°C

PARAMETER

TEST CONDITIONS

V_CCA

0.7 V

V_CCB

0.7 V

MIN

TYP

2.2

MAX UNIT

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

2.1

Power Dissipation Capacitance

per transceiver (A to B: outputs

enabled)

2.1

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

2.0

2.1

2.3

1.5

Power Dissipation Capacitance

per transceiver (A to B: outputs

disabled)

1.4

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

1.4

1.6

C_pdA

12.1

12.4

13.0

14.2

17.4

20.1

1.1

Power Dissipation Capacitance

per transceiver (B to A: outputs

enabled)

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

1.1

Power Dissipation Capacitance

per transceiver (B to A: outputs

disabled)

1.1

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

1.1

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MAX UNIT

6.14 Operating Characteristics: T_A= 25°C (continued)

PARAMETER

TEST CONDITIONS

V_CCA

V_CCB

0.7 V

MIN

TYP

12.1

12.4

12.9

14.1

17.2

20.1

1.1

1.2

1.8

1.7

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

Power Dissipation Capacitance

per transceiver (A to B: outputs

enabled)

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

Power Dissipation Capacitance

per transceiver (A to B: outputs

disabled)

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

C_pdB

Power Dissipation Capacitance

per transceiver (B to A: outputs

enabled)

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

2.5

1.1

1.8

1.7

Power Dissipation Capacitance

per transceiver (B to A: outputs

disabled)

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

2.1

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6.15 Typical Characteristics

3.4

3.2

1.25

1.2

V_CC= 1.8V

V_CC= 2.5V

V_CC= 3.3V

1.15

1.1

1.05

2.8

2.6

2.4

2.2

0.95

0.9

0.85

0.8

0.75

0.7

1.8

1.6

1.4

0.65

0.6

V_CC= 0.7V

V_CC= 1.2V

0.55

0.5

1.5

2.5

I_OH(mA)

3.5

4.5

I_OH(mA)

D001

图6-2. Typical (T_A=25°C) Output High Voltage (V_OH

)

图6-1. Typical (T_A=25°C) Output High Voltage (V_OH

vs Source Current (I_OH

)

vs Source Current (I_OH

)

700

650

600

550

500

450

400

350

300

250

200

150

100

220

200

180

160

140

120

100

V_CC= 1.8V

V_CC= 2.5V

V_CC= 3.3V

V_CC= 0.7V

V_CC= 1.2V

-50

I_OL(mA)

0.5

1.5

2.5

I_OL(mA)

3.5

4.5

D001

图6-3. Typical (T_A=25°C) Output High Voltage (V_OL) 图6-4. Typical (T_A=25°C) Output High Voltage (V_OL

)

vs Sink Current (I_OL

)

vs Sink Current (I_OL)

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7 Parameter Measurement Information

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

• f = 1 MHz

• Z_O= 50 Ω

• dv/dt ≤1 ns/V

Measurement Point

2 x V_CCO

Open

GND

R_L

Output Pin

Under Test

(1)

C_L

R_L

A. C_Lincludes probe and jig capacitance.

图7-1. Load Circuit

表7-1. Load Circuit Conditions

Parameter

V_CCO

R_L

C_L

S₁

V_TP

N/A

Δt/

Δv

Input transition rise or fall rate

15 pF

Open

0.65 V –3.6 V

1.1 V –3.6 V

1 MΩ

2 kΩ

20 kΩ

t_pd

Propagation (delay) time

0.65 V –0.95

15 pF

2 × V_CCO

0.3 V

0.15 V

0.1 V

3 V –3.6 V

1.65 V –2.7 V

1.1 V –1.6 V

2 kΩ

t_en, t_disEnable time, disable time

0.65 V –0.95

15 pF

2 × V_CCO

0.1 V

20 kΩ

15 pF

GND

0.3 V

0.15 V

0.1 V

3 V –3.6 V

1.65 V –2.7 V

1.1 V –1.6 V

2 kΩ

t_en, t_disEnable time, disable time

0.65 V –0.95

15 pF

GND

0.1 V

20 kΩ

(1)

V_CCI

(1)

V_CCI

Input A, B

100 kHz

V_CCI/ 2

Input A, B

500 ps/V œ 100 ns/V

0 V

V_OH

0 V

V_OH

(2)

t_pd

(2)

Output B, A

Ensure Monotonic

Rising and Falling Edge

(2)

V_OL

Output B, A

V_CCI/ 2

(2)

V_OL

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur

with specified R_L, C_L, and S₁

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur

with specified R_L, C_L, and S₁

图7-3. Input Transition Rise or Fall Rate

图7-2. Propagation Delay

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V_CCA

V_CCA/ 2

GND

t_dis

t_en

(3)

V_CCO

Output⁽¹⁾

V_CCO/ 2

V_OL+ V_TP

(4)

V_OL

V_OH

V_OH- V_TP

Output⁽²⁾

V_CCO/ 2

GND

A. Output waveform on the condition that input is driven to a valid Logic Low.

B. Output waveform on the condition that input is driven to a valid Logic High.

C. V_CCOis the supply pin associated with the output port.

D. V_OHand V_OLare typical output voltage levels with specified R_L, C_L, and S₁.

图7-4. Enable Time And Disable Time

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8 Detailed Description

8.1 Overview

The SN74AXC4T245-Q1 AEC-Q100 qualified device is a 4-bit, dual-supply noninverting bidirectional voltage

level translation device. Ax pins and control pins (1DIR, 2DIR,1 OE, and 2 OE) are referenced to V_CCAlogic

levels, and Bx pins are referenced to V_CCBlogic levels. The A port is able to accept I/O voltages ranging from

0.65 V to 3.6 V, while the B port can accept I/O voltages from 0.65 V to 3.6 V. A high on DIR allows data

transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When

OE is set to high, both Ax and Bx pins are in the high-impedance state. See Device Functional Modes for a

summary of the operation of the control logic.

8.2 Functional Block Diagram

One of Two Transceiver Pairs

V_CCA

V_CCB

xDIR

xOE

xB1

xB2

xA1

xA2

8.3 Feature Description

8.3.1 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input

capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum

input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the

Electrical Characteristics, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating

Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a

device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.

8.3.2 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device

creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.

Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without

being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at

all times.

8.3.3 Partial Power Down (I_off)

The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting

current backflow into the device. The maximum leakage into or out of any input or output pin on the device is

specified by I_offin the Electrical Characteristics.

8.3.4 V_CCIsolation

The inputs and outputs for this device enter a high-impedance state when either supply is <100 mV.

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8.3.5 Over-Voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum

input voltage value specified in the Recommended Operating Conditions.

8.3.6 Glitch-Free Power Supply Sequencing

Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where the

output erroneously transitions to VCC when it should be held low). Glitches of this nature can be misinterpreted

by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a false device

configuration of the peripheral, or even a false data initialization by the peripheral. For more information

regarding the power up glitch performance of the AXC family of level translators, see Glitch Free Power

Sequencing With AXC Level Translators.

8.3.7 Negative Clamping Diodes

The inputs and outputs to this device have negative clamping diodes as depicted in 图8-1.

CAUTION

Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to

the device. The input negative-voltage and output voltage ratings may be exceeded if the input and

output clamp-current ratings are observed.

V_CC

Device

Input

Output

Logic

GND

-I_IK

-I_OK

图8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.8 Fully Configurable Dual-Rail Design

Both the V_CCAand V_CCBpins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for

translating between any of the voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V).

8.3.9 Supports High-Speed Translation

The SN74AXC4T245-Q1 device can support high data-rate applications. The translated signal data rate can be

up to 380 Mbps when the signal is translated from 1.8 V to 3.3 V.

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8.3.10 Wettable Flanks

This device includes wettable flanks for at least one package. See the Features section on the front page of the

data sheet for which packages include this feature.

Package

Solder

Standard Lead

We able Flank Lead

Pad

PCB

图8-2. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After

Soldering

Wettable flanks help improve side wetting after soldering which makes QFN packages easier to inspect with

automatic optical inspection (AOI). A wettable flank can be dimpled or step-cut to provide additional surface area

for solder adhesion which assists in reliably creating a side fillet as shown in 图 8-2. Please see the mechanical

drawing for additional details.

8.4 Device Functional Modes

表8-1. Function Table (Each 2-Bit Section)

CONTROL INPUTS^{(1) (2)}

PORT STATUS

OPERATION

OE DIR

A PORT

B PORT

Input (Hi-Z)

Output (Enabled)

Input (Hi-Z)

B data to A bus

A data to B bus

Isolation

Output (Enabled)

Input (Hi-Z)

(1) Input circuits of the data I/Os are always active.

(2) Pins configured as inputs should not be left floating.

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9 Application and Implementation

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The AEC-Q100 qualified SN74AXC4T245-Q1 device can be used in level-translation applications for interfacing

devices or systems operating at different interface voltages with one another. The SN74AXC4T245-Q1 device is

ideal for use in applications where a push-pull driver is connected to the data I/Os. The maximum data rate can

be up to 380 Mbps when device translates a signal from 1.8 V to 3.3 V.

图 9-1 shows an example application where the SN74AXC4T245-Q1 device is used to translate a low voltage

UART signal from an SoC to a higher voltage signal which properly drives the inputs of the Bluetooth^®module,

and vice versa.

9.2 Typical Application

Pullup Resistors keep device disabled

during power up. OE inputs may also

be tied to GND to keep device enabled

0.7 V

3.3 V

0.1 µF

V_CCA

V_CCB

1DIR

2DIR

1OE

GPIO1

Bluetooth

Module

SN74AXC4T245-Q1

GPIO2

SoC

2OE

1A1

1A2

2A1

2A2

RTS

1B1

CTS

1B2

2B1

2B2

RTS

CTS

GND

图9-1. UART Interface Application

9.2.1 Design Requirements

For this design example, use the parameters listed in 表9-1.

表9-1. Design Parameters

DESIGN PARAMETERS

Input voltage range

EXAMPLE VALUES

0.65 V to 3.6 V

Output voltage range

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9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

• Input voltage range:

– Use the supply voltage of the device that is driving the SN74AXC4T245-Q1 device to determine the input

voltage range. For a valid logic-high, the value must exceed the high-level input voltage (V_IH) of the input

port. For a valid logic low the value must be less than the low-level input voltage (V_IL) of the input port.

• Output voltage range:

– Use the supply voltage of the device that the SN74AXC4T245-Q1 device is driving to determine the output

voltage range.

9.2.3 Application Curve

图9-2. Up Translation at 2.5 MHz (0.7 V to 3.3 V)

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10 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing

without any supply sequencing requirements such as ramp order or ramp rate.

This device was designed with various power supply sequencing methods in mind to help prevent unintended

triggering of downstream devices. For more information regarding the power up glitch performance of the AXC

family of level translators, see Glitch Free Power Sequencing With AXC Level Translators.

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:

• Use bypass capacitors on the power supply pins and place them as close to the device as possible.

• Use short trace lengths to avoid excessive loading.

11.2 Layout Example

Legend

Via to V_CCA

Via to V_CCB

Via to GND

Copper Traces

SN74AXC4T245-Q1PW

0.1µF

V_CCA

V_CCB

1DIR

2DIR

1A1

1OE

2OE

1B1

1B2

2B1

2B2

GND

RX to Module

TX from SoC

RTS from SoC

RX to SoC

CTS to Module

TX from Module

RTS from Module

1A2

2A1

CTS to SoC

2A2

GND

图11-1. Layout Example

Submit Document Feedback

Product Folder Links: SN74AXC4T245-Q1

SN74AXC4T245-Q1

ZHCSK08E –JULY 2019 –REVISED DECEMBER 2021

www.ti.com.cn

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Glitch Free Power Sequencing With AXC Level Translators application report

• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report

• Texas Instruments, Low Voltage Translation For Standard Interfaces application report

• Texas Instruments, Power Sequencing for AXC Family of Devices application report

• Texas Instruments, SN74AXC4T245RSV EVM evaluation module user's guide

• Texas Instruments, UART Interface Using SN74AXC4T245 video

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

Bluetooth^®is a registered trademark of Bluetooth Special Interest Group (SIG).

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: SN74AXC4T245-Q1

PACKAGE OPTION ADDENDUM

www.ti.com

16-Mar-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

CAXC4T245QBQBRQ1

CAXC4T245QRSVRQ1

CAXC4T245QWBQBRQ1

H14T245QRSVRQ1-NT

SN74AXC4T245QPWRQ1

ACTIVE

WQFN

UQFN

WQFN

UQFN

TSSOP

BQB

RSV

BQB

RSV

3000 RoHS & Green

2000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

4T245Q

Samples

NIPDAUAG

NIPDAU

1ZDR

4T245Q

1ZDR

NIPDAUAG

NIPDAU

4T245Q

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

16-Mar-2023

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AXC4T245-Q1 :

Catalog : SN74AXC4T245

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CAXC4T245QBQBRQ1

CAXC4T245QRSVRQ1

WQFN

UQFN

BQB

RSV

BQB

RSV

3000

2000

180.0

178.0

180.0

330.0

12.4

13.5

12.4

9.5

2.8

2.1

2.8

2.1

6.9

3.8

2.9

3.8

2.9

5.6

1.2

0.75

1.2

4.0

8.0

12.0

8.0

CAXC4T245QWBQBRQ1 WQFN

H14T245QRSVRQ1-NT UQFN

SN74AXC4T245QPWRQ1 TSSOP

0.75

1.6

12.4

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CAXC4T245QBQBRQ1

CAXC4T245QRSVRQ1

CAXC4T245QWBQBRQ1

H14T245QRSVRQ1-NT

SN74AXC4T245QPWRQ1

WQFN

UQFN

WQFN

UQFN

TSSOP

BQB

RSV

BQB

RSV

3000

2000

210.0

189.0

210.0

189.0

356.0

185.0

356.0

35.0

36.0

35.0

36.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

BQB 16

2.5 x 3.5, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226161/A

www.ti.com

PACKAGE OUTLINE

WQFN - 0.8 mm max height

PLASTIC QUAD FLAT PACK-NO LEAD

BQB0016A

2.6

2.4

3.6

3.4

PIN 1 INDEX AREA

0.8

0.7

SEATING PLANE

0.08 C

1.1

0.9

0.05

0.00

(0.2) TYP

2X 0.5

10X 0.5

SYMM

2.5

2.1

1.9

0.30

0.18

16X

0.5

0.3

PIN 1 ID

(OPTIONAL)

SYMM

16X

0.1

C A B

0.05

4224640/A 11/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

WQFN - 0.8 mm max height

BQB0016A

PLASTIC QUAD FLAT PACK-NO LEAD

(2.3)

(1)

2X (0.5)

10X (0.5)

SYMM

(2.5)

(2)

(3.3)

(0.75)

16X (0.24)

16X (0.6)

(Ø0.2) VIA

TYP

SYMM

(R0.05) TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

0.07 MIN

ALL AROUND

METAL

EXPOSED METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

EXPOSED METAL

NON-SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

4224640/A 11/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271)

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

WQFN - 0.8 mm max height

BQB0016A

PLASTIC QUAD FLAT PACK-NO LEAD

(2.3)

(0.95)

2X (0.5)

10X (0.5)

SYMM

(2.5)

(1.79) (3.3)

16X (0.24)

16X (0.6)

EXPOSED METAL

SYMM

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

85% PRINTED COVERAGE BY AREA

SCALE: 20X

4224640/A 11/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

WQFN - 0.8 mm max height

INDSTNAME

BQB0016B

2.6

2.4

PIN 1 INDEX AREA

3.6

3.4

0.1 MIN

(0.13)

SECTION A-A

TYPICAL

0.8 MAX

SEATING PLANE

0.05

0.00

0.08 C

1.1

0.9

2X 0.5

(0.2) TYP

10X 0.5

(0.16)

SYMM

2.5

2.1

1.9

0.3

16X

0.2

0.1

0.05

C A B

PIN 1 ID

(OPTIONAL)

0.5

0.3

16X

SYMM

4226135/A 08/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

WQFN - 0.8 mm max height

INDSTNAME

BQB0016B

(2.3)

(1)

16X (0.6)

16X (0.25)

10X (0.5)

SYMM

(2)

(3.3)

2X (0.75)

(R0.05) TYP

(Ø 0.2) VIA

TYP

2X (0.5)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

4226135/A 08/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271)

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

WQFN - 0.8 mm max height

INDSTNAME

BQB0016B

(2.3)

(0.95)

16X (0.6)

16X (0.25)

10X (0.5)

SYMM

(1.79)

(3.3)

2X (0.75)

(R0.05) TYP

METAL TYP

2X (0.5)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

85% PRINTED COVERAGE BY AREA

SCALE: 20X

4226135/A 08/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

RSV0016A

UQFN - 0.55 mm max height

ULTRA THIN QUAD FLATPACK - NO LEAD

1.85

1.75

PIN 1 INDEX AREA

2.65

2.55

0.55

0.45

SEATING PLANE

0.05 C

0.05

0.00

2X 1.2

SYMM

℄

(0.13) TYP

0.45

0.35

15X

SYMM

℄

2X 1.2

12X 0.4

0.25

16X

0.15

0.07

0.05

C A B

0.55

0.45

PIN 1 ID

(45° X 0.1)

4220314/C 02/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

RSV0016A

UQFN - 0.55 mm max height

ULTRA THIN QUAD FLATPACK - NO LEAD

SYMM

℄

(0.7)

SEE SOLDER MASK

DETAIL

16X (0.2)

SYMM

℄

12X (0.4)

(2.4)

(R0.05) TYP

15X (0.6)

(1.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 25X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4220314/C 02/2020

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RSV0016A

UQFN - 0.55 mm max height

ULTRA THIN QUAD FLATPACK - NO LEAD

(0.7)

16X (0.2)

SYMM

℄

12X (0.4)

(2.4)

(R0.05) TYP

15X (0.6)

SYMM

℄

(1.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 25X

4220314/C 02/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SEATING

PLANE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX AREA

14X 0.65

5.1

4.9

4.55

NOTE 3

0.30

16X

4.5

4.3

NOTE 4

1.2 MAX

0.19

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 -8

DETAIL A

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

16X (1.5)

(R0.05) TYP

16X (0.45)

SYMM

14X (0.65)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

16X (1.5)

SYMM

(R0.05) TYP

16X (0.45)

SYMM

14X (0.65)

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN74AXC4T245QPWRQ1 [TI]

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