SN74AXC4T245RSVR [TI]

4 位双电源总线收发器 | RSV | 16 | -40 to 125;


型号：	SN74AXC4T245RSVR
厂家：	TEXAS INSTRUMENTS
描述：	4 位双电源总线收发器 \| RSV \| 16 \| -40 to 125 总线收发器
文件：	总40页 (文件大小：2351K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74AXC4T245

_{SCES877A – DECEMBER 2018 –}S_REN_V7_IS4_EA_DX_JC_UL4_YT₂2₀4₂5₀

SCES877A – DECEMBER 2018 – REVISED JULY 2020

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SN74AXC4T245 Four-Bit Bus Transceiver with Configurable Voltage Translation

and Tri-State Outputs

The SN74AXC4T245 device is designed for

asynchronous communication between data buses.

1 Features

•

Fully Configurable Dual-Rail Design Allows Each

Port to Operate With a Power Supply Range From

0.65 V to 3.6 V

Operating Temperature From –40°C to +125°C

Multiple Direction Control Pins to Allow

Simultaneous Up and Down Translation

Glitch-Free Power Supply Sequencing

Up to 380 Mbps Support When Translating from

1.8 V to 3.3 V

The device transmits data from the A bus to the B bus

or from the B bus to the A bus, depending on the logic

level of the direction-control inputs (1DIR and 2DIR).

The output-enable inputs (1 OE and 2 OE) are used

to disable the outputs so the buses are effectively

isolated. The SN74AXC4T245 device is designed so

the control pins (xDIR and x OE) are referenced to

•

V_CCA

To ensure the high-impedance state of the level shifter

I/Os during power up or power down, the x OE pins

should be tied to V_CCAthrough a pullup resistor.

•

V_CCIsolation Feature

– If Either V_CCInput is Below 100 mV, All I/Os

Outputs are Disabled and Become High-

Impedance

I_offSupports Partial-Power-Down Mode Operation

Compatible With AVC Family Level Shifters

Latch-Up Performance Exceeds 100 mA Per JESD

78, Class II

This device is fully specified for partial-power-down

applications using the I_offcurrent. The I_offprotection

circuitry ensures that no excessive current is drawn

from or to an input, output, or combined I/O that is

biased to a specific voltage while the device is

powered down.

•

ESD Protection Exceeds JESD 22

– 8000-V Human-Body Model

– 1000-V Charged-Device Model

The V_CCisolation feature ensures that if either V_CCA

or V_CCBis less than 100 mV, both I/O ports enter a

high-impedance state by disabling their outputs.

Glitch-Free power supply sequencing allows either

supply rail to be powered on or off in any order while

providing robust power sequencing performance.

2 Applications

•

Enterprise and Communications

Industrial

Personal Electronics

Wireless Infrastructure

Building Automation

Point of Sale

Device Information

PART NUMBER

SN74AXC4T245PW

SN74AXC4T245BQB

PACKAGE⁽¹⁾

BODY SIZE (NOM)

TSSOP (16)

5.00 mm x 4.40 mm

WQFN (16)

2.50 mm x 3.50 mm

2.60 mm x 1.80 mm

3 Description

SN74AXC4T245RSV UQFN (16)

The SN74AXC4T245 is a four-bit noninverting bus

transceiver that uses two individually configurable

power-supply rails. The device is operational with both

V_CCAand V_CCBsupplies as low as 0.65 V. The A port

is designed to track V_CCA, which accepts any supply

voltage from 0.65 V to 3.6 V. The B port is designed to

track V_CCB, which also accepts any supply voltage

from 0.65 V to 3.6 V. Additionally the SN74AXC4T245

is compatible with a single-supply system.

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

One of Two Transceiver Pairs

V_CCA

V_CCB

xDIR

xOE

xB1

xB2

xA1

xA2

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Switching Characteristics, V_CCA= 0.7 V..................... 7

6.7 Switching Characteristics, V_CCA= 0.8 V..................... 8

6.8 Switching Characteristics, V_CCA= 0.9 V..................... 9

6.9 Switching Characteristics, V_CCA= 1.2 V................... 10

6.10 Switching Characteristics, V_CCA= 1.5 V................. 11

6.11 Switching Characteristics, V_CCA= 1.8 V................. 12

6.12 Switching Characteristics, V_CCA= 2.5 V................. 13

6.13 Switching Characteristics, V_CCA= 3.3 V................. 14

6.14 Operating Characteristics: T_A= 25°C..................... 15

7 Parameter Measurement Information..........................17

7.1 Load Circuit and Voltage Waveforms........................17

8 Detailed Description......................................................19

8.1 Overview...................................................................19

8.2 Functional Block Diagram.........................................19

8.3 Feature Description...................................................19

8.4 Device Functional Modes..........................................20

9 Application and Implementation..................................21

9.1 Application Information............................................. 21

9.2 Typical Application.................................................... 21

10 Power Supply Recommendations..............................23

11 Layout...........................................................................23

11.1 Layout Guidelines................................................... 23

11.2 Layout Example...................................................... 23

12 Device and Documentation Support..........................24

12.1 Documentation Support.......................................... 24

12.2 Receiving Notification of Documentation Updates..24

12.3 Support Resources................................................. 24

12.4 Trademarks.............................................................24

12.5 Electrostatic Discharge Caution..............................24

12.6 Glossary..................................................................24

13 Mechanical, Packaging, and Orderable

Information.................................................................... 25

4 Revision History

Changes from Revision * (December 2018) to Revision A (July 2020)

Page

Updated the numbering format for tables, figures and cross-references throughout the document...................1

Added BQB (WQFN) package option to Device Information table .................................................................... 1

•

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5 Pin Configuration and Functions

V_CCA

1DIR

2DIR

1A1

V_CCB

1OE

2OE

1B1

1B2

2B1

2B2

GND

1DIR

2DIR

1A1

1A2

2A1

2A2

1OE

2OE

13 1B1

12 1B2

11 2B1

10 2B2

Thermal

Pad

1A2

2A1

2A2

GND

Figure 5-1. PW Package 16-Pin TSSOP Top View

Figure 5-2. BQB Package 16-Pin WQFN

Transparent Top View

16 15 14 13

2B2

1OE

V_CCB

GND

2A2

V_CCA

1DIR

Figure 5-3. RSV Package 16-Pin UQFN Transparent Top View

Pin Functions

NAME

NO.

TYPE

DESCRIPTION

RSV

BQB

1A1

1A2

1B1

1B2

1DIR

I/O

Input/output 1A1. Referenced to V_CCA

Input/output 1A2. Referenced to V_CCA

Input/output 1B1. Referenced to V_CCB

Input/output 1B2. Referenced to V_CCB

Direction-control input for ‘1’ ports.

Tri-state output-mode enable. Pull OE high to place ‘1’ outputs

in tri-state mode. Referenced to V_CCA

1 OE

2A1

2A2

2B1

2B2

2DIR

I/O

Input/output 2A1. Referenced to V_CCA

Input/output 2A2. Referenced to V_CCA

Input/output 2B1. Referenced to V_CCB

Input/output 2B2. Referenced to V_CCB

Direction-control input for ‘2’ ports.

Tri-state output-mode enable. Pull OE high to place ‘2’ outputs

2 OE

in tri-state mode. Referenced to V_CCA

GND

V_CCA

V_CCB

8, 9

10, 11

8, 9

—

Ground.

A-port power supply voltage. 0.65 V ≤ V_CCA≤ 3.6 V.

B-port power supply voltage. 0.65 V ≤ V_CCB≤ 3.6 V.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX UNIT

V_CCASupply voltage A

V_CCBSupply voltage B

4.2

I/O Ports (A Port)

I/O Ports (B Port)

Control Inputs

A Port

V_I

Input Voltage⁽²⁾

V_O

Voltage applied to any output in the high-impedance or power-off state⁽²⁾

Voltage applied to any output in the high or low state^{(2) (3)}

B Port

A Port

–0.5 V_CCA+ 0.2

–0.5 V_CCB+ 0.2

–50

B Port

I_IK

I_OK

I_O

Input clamp current

V_I< 0

Output clamp current

V_O< 0

–50

Continuous output current

Continuous current through V_CCor GND

Junction Temperature

–50

50 mA

100 mA

150 °C

–100

T_j

T_stg

Storage temperature

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.

6.2 ESD Ratings

VALUE

±8000

±1000

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

0.65

MAX UNIT

V_CCA

V_CCB

Supply voltage A

Supply voltage B

3.6

0.65

V_CCI= 0.65 V - 0.75 V

V_CCI= 0.76 V - 1 V

V_CCI= 1.1 V - 1.95 V

V_CCI= 2.3 V - 2.7 V

V_CCI= 3 V - 3.6 V

V_CCIx 0.70

V_CCIx 0.65

1.6

Data Inputs

V_IH

High-level input voltage

V_CCA= 0.65 V - 0.75 V

V_CCA= 0.76 V - 1 V

V_CCA= 1.1 V - 1.95 V

V_CCA= 2.3 V - 2.7 V

V_CCA= 3 V - 3.6 V

V_CCI= 0.65 V - 0.75 V

V_CCI= 0.76 V - 1 V

V_CCI= 1.1 V - 1.95 V

V_CCI= 2.3 V - 2.7 V

V_CCI= 3 V - 3.6 V

V_CCAx 0.70

V_CCAx 0.65

1.6

Control Inputs(xDIR, x OE)

Referenced to V_CCA

V_CCIx 0.30

V_CCIx 0.35

0.7

Data Inputs

0.8

V_IL

Low-level input voltage

V_CCA= 0.65 V - 0.75 V

V_CCA= 0.76 V - 1 V

V_CCA= 1.1 V - 1.95 V

V_CCA= 2.3 V - 2.7 V

V_CCA= 3 V - 3.6 V

V_CCAx 0.30

V_CCAx 0.35

0.7

Control Inputs(xDIR, x OE)

Referenced to V_CCA

0.8

V_I

Input voltage ⁽²⁾

Output voltage

3.6

Active State

Tri-State

V_CCO

V_O

3.6

Δt/Δv⁽²⁾Input transition rate

10 ns/V

125 °C

T_AOperating free-air temperature

–40

(1) V_CCIis the V_CCassociated with the input port. V_CCOis the V_CCassociated with the output port.

(2) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs.

6.4 Thermal Information

SN74AXC4T245

THERMAL METRIC⁽¹⁾

PW (TSSOP) RSV (UQFN) BQB (WQFN)

UNIT

16 PINS

126.9

49.3

74.3

8.1

16 PINS

130.1

70.3

57.4

4.6

16 PINS

73.0

35.1

42.8

4.6

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

ψ_JB

73.4

55.8

42.8

10.2

R_θJC(bottom)Junction-to-case (bottom) thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) ^{(1) (2)}

Operating free-air temperature (T_A)

PARAMETER

TEST CONDITIONS

V_CCA

V_CCB

–40°C to 85°C

MIN TYP⁽⁴⁾

–40°C to 125°C

MIN TYP⁽⁴⁾

UNIT

MAX

V_CCO

–

V_CCO

–

I_OH= –100 µA

0.7 V - 3.6 V

0.1

I_OH= –50 µA

I_OH= –200 µA

I_OH= –500 µA

0.65 V

0.76 V

0.85 V

1.1 V

0.65 V

0.76 V

0.85 V

1.1 V

0.55

0.58

0.65

0.85

1.05

1.2

0.55

0.58

0.65

0.85

1.05

1.2

High-level output

voltage

V_OH

V_I= V_IH

I_OH= –3 mA

I_OH= –6 mA

I_OH= –8 mA

I_OH= –9 mA

I_OH= –12 mA

I_OL= 100 µA

I_OL= 50 µA

I_OL= 200 µA

I_OL= 500 µA

I_OL= 3 mA

1.4 V

1.65 V

2.3 V

1.65 V

2.3 V

1.75

2.3

1.75

2.3

3 V

0.7 V - 3.6 V

0.65 V

0.76 V

0.85 V

1.1 V

0.7 V - 3.6 V

0.65 V

0.76 V

0.85 V

1.1 V

0.1

0.18

0.2

0.18

0.2

Low-level output

voltage

V_OL

V_I= V_IL

0.25

0.35

0.45

0.55

0.7

0.25

0.35

0.45

0.55

0.7

I_OL= 6 mA

1.4 V

I_OL= 8 mA

1.65 V

2.3 V

1.65 V

2.3 V

I_OL= 9 mA

I_OL= 12 mA

3 V

Control inputs (xDIR, x OE): V_I

= V_CCAor GND

0.65 V- 3.6 V

–0.5

–4

0.5

–1

–8

µA

Input leakage

current

I_I

Data Inputs (xAx, xBx)

V_I= V_CCIor GND

0 V

0 V - 3.6 V

0 V

–4

–8

Partial power

down current

A or B Port

V_Ior V_O= 0 V - 3.6 V

I_off

µA

0 V - 3.6 V

A or B Port

Tri-state output

current ⁽³⁾

I_OZ

V_I= V_CCIor GND, V_O= V_CCO3.6 V

or GND, OE = V_IH

3.6 V

–4

–2

–8

0.65 V- 3.6 V

3.6 V

V_CCAsupply

current

V_I= V_CCI

or GND

I_CCA

I_O= 0

0 V

–12

µA

3.6 V

0 V

0.65 V- 3.6 V

0 V

0.65 V- 3.6 V

3.6 V

V_CCBsupply

current

V_I= V_CCI

or GND

I_CCB

I_O= 0

3.6 V

0 V

–2

–12

I_CCA

I_CCB

Combined

supply current

V_I= V_CCI

or GND

0.65 V- 3.6 V

3.3 V

0.65 V- 3.6 V

3.3 V

µA

Control input

capacitance

C_i

V_I= 3.3 V or GND

4.5

6.6

4.5

6.6

Data I/O

capacitance

OE = V_CCA, V_O= 1.65V DC +1

MHz -16 dBm sine wave

C_io

3.3 V

(1) V_CCIis the V_CCassociated with the input port.

(2) V_CCOis the V_CCassociated with the output port.

(3) For I/O ports, the parameter I_OZincludes the input leakage current.

(4) All typical data is taken at 25°C.

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6.6 Switching Characteristics, V_CCA= 0.7 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V 1.5 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

)

PARAMETER

FROM

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

0.5

155

156

154

238

286

0.5

108

128

156

121

238

194

0.5

185

Propagation

delay

t_pd

106

156

101

238

146

156

125

238

146

t_disDisable time

238

t_enEnable time

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6.7 Switching Characteristics, V_CCA= 0.8 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V 1.5 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

)

PARAMETER

FROM

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

0.5

128

108

103

143

243

0.5

Propagation

delay

t_pd

103

110

143

172

103

t_disDisable time

143

129

143

t_enEnable time

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6.8 Switching Characteristics, V_CCA= 0.9 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V 1.5 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

)

PARAMETER

FROM

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

0.5

106

0.5

Propagation

delay

t_pd

t_disDisable time

138

105

t_enEnable time

222

148

116

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6.9 Switching Characteristics, V_CCA= 1.2 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V 1.5 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

)

PARAMETER

FROM

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

0.5

Propagation

delay

t_pd

t_disDisable time

132

t_enEnable time

164

108

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6.10 Switching Characteristics, V_CCA= 1.5 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V 1.5 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

)

PARAMETER

FROM

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

0.5

Propagation

delay

t_pd

t_disDisable time

131

t_enEnable time

109

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6.11 Switching Characteristics, V_CCA= 1.8 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V 1.5 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

)

PARAMETER

FROM

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

0.5

Propagation

delay

t_pd

t_disDisable time

130

t_enEnable time

102

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6.12 Switching Characteristics, V_CCA= 2.5 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V 1.5 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

)

PARAMETER

FROM

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

0.5

Propagation

delay

t_pd

t_disDisable time

128

t_enEnable time

120

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6.13 Switching Characteristics, V_CCA= 3.3 V

See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.

B-Port Supply Voltage (V_CCB

Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V 1.5 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

)

PARAMETER

FROM

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

UNIT

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

0.5

Propagation

delay

t_pd

185

t_disDisable time

141

t_enEnable time

189

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6.14 Operating Characteristics: T_A= 25°C

PARAMETER

TEST CONDITIONS

V_CCA

0.7 V

V_CCB

0.7 V

MIN

TYP

2.2

MAX UNIT

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

2.1

Power Dissipation Capacitance

per transceiver (A to B: outputs

enabled)

2.1

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

2.0

2.1

2.3

1.5

Power Dissipation Capacitance

per transceiver (A to B: outputs

disabled)

1.4

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

1.4

1.6

C_pdA

12.1

12.4

13.0

14.2

17.4

20.1

1.1

Power Dissipation Capacitance

per transceiver (B to A: outputs

enabled)

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

1.1

Power Dissipation Capacitance

per transceiver (B to A: outputs

disabled)

1.1

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

1.1

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MAX UNIT

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PARAMETER

TEST CONDITIONS

V_CCA

0.7 V

V_CCB

0.7 V

MIN

TYP

12.1

12.4

12.9

14.1

17.2

20.1

1.1

1.2

1.8

1.7

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

Power Dissipation Capacitance

per transceiver (A to B: outputs

enabled)

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

Power Dissipation Capacitance

per transceiver (A to B: outputs

disabled)

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

C_pdB

Power Dissipation Capacitance

per transceiver (B to A: outputs

enabled)

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

2.5

1.1

1.8

1.7

Power Dissipation Capacitance

per transceiver (B to A: outputs

disabled)

CL = 0, RL = Open f = 1

MHz, tr = tf = 1 ns

2.1

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7 Parameter Measurement Information

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

•

f = 1 MHz

Z_O= 50 Ω

dv/dt ≤ 1 ns/V

Measurement Point

2 x V_CCO

Open

R_L

Output Pin

Under Test

GND

(1)

C_L

R_L

A. C_Lincludes probe and jig capacitance.

Figure 7-1. Load Circuit

Table 7-1. Load Circuit Conditions

Parameter

V_CCO

R_L

C_L

S₁

V_TP

N/A

Δt/Δv Input transition rise or fall rate

0.65 V – 3.6 V

1.1 V – 3.6 V

1 MΩ

2 kΩ

15 pF

Open

t_pd

Propagation (delay) time

0.65 V – 0.95

20 kΩ

15 pF

Open

N/A

3 V – 3.6 V

1.65 V – 2.7 V

1.1 V – 1.6 V

2 kΩ

15 pF

2 × V_CCO

0.3 V

0.15 V

0.1 V

t_en, t_disEnable time, disable time

0.65 V – 0.95

20 kΩ

15 pF

2 × V_CCO

0.1 V

3 V – 3.6 V

1.65 V – 2.7 V

1.1 V – 1.6 V

2 kΩ

15 pF

GND

0.3 V

0.15 V

0.1 V

t_en, t_disEnable time, disable time

0.65 V – 0.95

20 kΩ

15 pF

GND

0.1 V

(1)

V_CCI

(1)

V_CCI

Input A, B

100 kHz

V_CCI/ 2

Input A, B

500 ps/V œ 100 ns/V

0 V

V_OH

0 V

V_OH

(2)

t_pd

(2)

Output B, A

Ensure Monotonic

Rising and Falling Edge

(2)

V_OL

Output B, A

V_CCI/ 2

(2)

V_OL

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur with

specified R_L, C_L, and S₁

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur with

specified R_L, C_L, and S₁

Figure 7-3. Input Transition Rise or Fall Rate

Figure 7-2. Propagation Delay

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V_CCA

GND

V_CCA/ 2

t_dis

t_en

(3)

V_CCO

Output⁽¹⁾

V_CCO/ 2

V_OL+ V_TP

(4)

V_OL

(4)

V_OH

V_OH- V_TP

Output⁽²⁾

V_CCO/ 2

GND

A. Output waveform on the condition that input is driven to a valid Logic Low.

B. Output waveform on the condition that input is driven to a valid Logic High.

C. V_CCOis the supply pin associated with the output port.

D. V_OHand V_OLare typical output voltage levels with specified R_L, C_L, and S₁.

Figure 7-4. Enable Time And Disable Time

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8 Detailed Description

8.1 Overview

The SN74AXC4T245 is a 4-bit, dual-supply noninverting bidirectional voltage level translation device. Ax pins

and control pins (1DIR, 2DIR,1 OE, and 2 OE) are referenced to V_CCAlogic levels, and Bx pins are referenced to

V_CCBlogic levels. The A port is able to accept I/O voltages ranging from 0.65 V to 3.6 V, while the B port can

accept I/O voltages from 0.65 V to 3.6 V. A high on DIR allows data transmission from A to B and a low on DIR

allows data transmission from B to A when OE is set to low. When OE is set to high, both Ax and Bx pins are in

the high-impedance state. See Device Functional Modes for a summary of the operation of the control logic.

8.2 Functional Block Diagram

One of Two Transceiver Pairs

V_CCA

V_CCB

xDIR

xOE

xB1

xB2

xA1

xA2

8.3 Feature Description

8.3.1 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input

capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum

input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the

Electrical Characteristics, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating

Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a

device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.

8.3.2 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device

creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.

Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without

being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at

all times.

8.3.3 Partial Power Down (I_off)

The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting

current backflow into the device. The maximum leakage into or out of any input or output pin on the device is

specified by I_offin the Electrical Characteristics.

8.3.4 V_CCIsolation

The inputs and outputs for this device enter a high-impedance state when either supply is <100mV.

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8.3.5 Over-voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum

input voltage value specified in the Recommended Operating Conditions.

8.3.6 Glitch-free Power Supply Sequencing

Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where the

output erroneously transitions to VCC when it should be held low). Glitches of this nature can be misinterpreted

by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a false device

configuration of the peripheral, or even a false data initialization by the peripheral. For more information

regarding the power up glitch performance of the AXC family of level translators, see the Glitch Free Power

Sequencing With AXC Level Translators application report

8.3.7 Negative Clamping Diodes

The inputs and outputs to this device have negative clamping diodes as depicted in Figure 8-1.

CAUTION

Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to

the device. The input negative-voltage and output voltage ratings may be exceeded if the input and

output clamp-current ratings are observed.

V_CC

Device

Input

Output

Logic

GND

-I_IK

-I_OK

Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.8 Fully Configurable Dual-Rail Design

Both the V_CCAand V_CCBpins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for

translating between any of the voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V and 3.3 V).

8.3.9 Supports High-Speed Translation

The SN74AXC4T245 device can support high data-rate applications. The translated signal data rate can be up

to 380 Mbps when the signal is translated from 1.8 V to 3.3 V.

8.4 Device Functional Modes

Table 8-1. Function Table

(Each 2-Bit Section)

CONTROL INPUTS⁽¹⁾

PORT STATUS

A PORT

OPERATION

DIR

B PORT

Input (Hi-Z)

Output (Enabled)

Input (Hi-Z)

B data to A bus

A data to B bus

Isolation

Output (Enabled)

Input (Hi-Z)

(1) Input circuits of the data I/Os are always active.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The SN74AXC4T245 device can be used in level-translation applications for interfacing devices or systems

operating at different interface voltages with one another. The SN74AXC4T245 device is ideal for use in

applications where a push-pull driver is connected to the data I/Os. The max data rate can be up to 380 Mbps

when device translates a signal from 1.8 V to 3.3 V.

One example application is shown in Figure 9-1, where the SN74AXC4T245 device is used to translate a low

voltage UART signal from an SoC to a higher voltage signal which properly drive the inputs of the bluetooth

module, and vice versa.

9.2 Typical Application

Pullup Resistors keep device disabled

during power up. OE inputs may also

be tied to GND to keep device enabled

0.7 V

3.3 V

0.1 µF

V_CCA

V_CCB

1DIR

2DIR

1OE

GPIO1

Bluetooth

Module

GPIO2

SoC

SN74AXC4T245

2OE

1A1

1A2

2A1

2A2

RTS

1B1

CTS

1B2

2B1

2B2

RTS

CTS

GND

Figure 9-1. UART Interface Application

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1.

Table 9-1. Design Parameters

DESIGN PARAMETERS

Input voltage range

EXAMPLE VALUES

0.65 V to 3.6 V

Output voltage range

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9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

•

Input voltage range

– Use the supply voltage of the device that is driving the SN74AXC4T245 device to determine the input

voltage range. For a valid logic-high, the value must exceed the high-level input voltage (V_IH) of the input

port. For a valid logic low the value must be less than the low-level input voltage (V_IL) of the input port.

Output voltage range

•

– Use the supply voltage of the device that the SN74AXC4T245 device is driving to determine the output

voltage range.

9.2.3 Application Curve

Figure 9-2. Up Translation at 2.5 MHz (0.7 V to 3.3 V)

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10 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing

without any supply sequencing requirements such as ramp order or ramp rate.

This device was designed with various power supply sequencing methods in mind to help prevent unintended

triggering of downstream devices. For more information regarding the power up glitch performance of the AXC

family of level translators, see the Glitch Free Power Sequencing With AXC Level Translators application report

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:

•

Use bypass capacitors on the power supply pins and place them as close to the device as possible.

Use short trace lengths to avoid excessive loading.

11.2 Layout Example

Legend

Via to V_CCA

Via to V_CCB

Via to GND

Copper Traces

SN74AXC4T245PW

0.1µF

V_CCA

1DIR

2DIR

1A1

V_CCB

1OE

2OE

1B1

1B2

2B1

2B2

GND

RX to Module

TX from SoC

RTS from SoC

RX to SoC

CTS to Module

TX from Module

RTS from Module

1A2

2A1

CTS to SoC

2A2

GND

Figure 11-1. Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

Texas Instruments, Implications of Slow or Floating CMOS Inputs application report

Texas Instruments, Power Sequencing for AXC Family of Devices application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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11-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SN74AXC4T245BQBR

SN74AXC4T245PWR

SN74AXC4T245RSVR

ACTIVE

WQFN

TSSOP

UQFN

BQB

3000 RoHS & Green

2000 RoHS & Green

3000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

4T245

NIPDAU | SN

NIPDAUAG

SN4T245

1TIR

RSV

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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11-Dec-2020

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AXC4T245 :

Automotive: SN74AXC4T245-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Dec-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74AXC4T245BQBR

SN74AXC4T245PWR

SN74AXC4T245RSVR

WQFN

TSSOP

UQFN

BQB

3000

2000

3000

180.0

330.0

178.0

12.4

13.5

2.8

6.9

2.1

3.8

5.6

2.9

1.2

1.6

4.0

8.0

4.0

12.0

1.6

RSV

0.75

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Dec-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74AXC4T245BQBR

SN74AXC4T245PWR

SN74AXC4T245RSVR

WQFN

TSSOP

UQFN

BQB

3000

2000

3000

210.0

364.0

853.0

189.0

185.0

364.0

449.0

185.0

35.0

27.0

35.0

36.0

RSV

Pack Materials-Page 2

PACKAGE OUTLINE

RSV0016A

UQFN - 0.55 mm max height

ULTRA THIN QUAD FLATPACK - NO LEAD

1.85

1.75

PIN 1 INDEX AREA

2.65

2.55

0.55

0.45

SEATING PLANE

0.05 C

0.05

0.00

2X 1.2

SYMM

℄

(0.13) TYP

0.45

0.35

15X

SYMM

℄

2X 1.2

12X 0.4

0.25

16X

0.15

0.07

0.05

C A B

0.55

0.45

PIN 1 ID

(45° X 0.1)

4220314/C 02/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

RSV0016A

UQFN - 0.55 mm max height

ULTRA THIN QUAD FLATPACK - NO LEAD

SYMM

℄

(0.7)

SEE SOLDER MASK

DETAIL

16X (0.2)

SYMM

℄

12X (0.4)

(2.4)

(R0.05) TYP

15X (0.6)

(1.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 25X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4220314/C 02/2020

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RSV0016A

UQFN - 0.55 mm max height

ULTRA THIN QUAD FLATPACK - NO LEAD

(0.7)

16X (0.2)

SYMM

℄

12X (0.4)

(2.4)

(R0.05) TYP

15X (0.6)

SYMM

℄

(1.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 25X

4220314/C 02/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SEATING

PLANE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX AREA

14X 0.65

5.1

4.9

4.55

NOTE 3

0.30

16X

4.5

4.3

NOTE 4

1.2 MAX

0.19

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 -8

DETAIL A

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

16X (1.5)

(R0.05) TYP

16X (0.45)

SYMM

14X (0.65)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

16X (1.5)

SYMM

(R0.05) TYP

16X (0.45)

SYMM

14X (0.65)

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

BQB 16

2.5 x 3.5, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226161/A

www.ti.com

PACKAGE OUTLINE

WQFN - 0.8 mm max height

PLASTIC QUAD FLAT PACK-NO LEAD

BQB0016A

2.6

2.4

3.6

3.4

PIN 1 INDEX AREA

0.8

0.7

SEATING PLANE

0.08 C

1.1

0.9

0.05

0.00

(0.2) TYP

2X 0.5

10X 0.5

SYMM

2.5

2.1

1.9

0.30

0.18

16X

0.5

0.3

PIN 1 ID

(OPTIONAL)

SYMM

16X

0.1

C A B

0.05

4224640/A 11/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

WQFN - 0.8 mm max height

BQB0016A

PLASTIC QUAD FLAT PACK-NO LEAD

(2.3)

(1)

2X (0.5)

10X (0.5)

SYMM

(2.5)

(2)

(3.3)

(0.75)

16X (0.24)

16X (0.6)

(Ø0.2) VIA

TYP

SYMM

(R0.05) TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

0.07 MIN

ALL AROUND

METAL

EXPOSED METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

EXPOSED METAL

NON-SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

4224640/A 11/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271)

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

WQFN - 0.8 mm max height

BQB0016A

PLASTIC QUAD FLAT PACK-NO LEAD

(2.3)

(0.95)

2X (0.5)

10X (0.5)

SYMM

(2.5)

(1.79) (3.3)

16X (0.24)

16X (0.6)

EXPOSED METAL

SYMM

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

85% PRINTED COVERAGE BY AREA

SCALE: 20X

4224640/A 11/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN74AXC4T245RSVR [TI]

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