SN74BCT29834_11 [TI]
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER;
| 型号： | SN74BCT29834_11 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER |
| 文件： | 总7页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74BCT29834
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993
DW OR NT PACKAGE
(TOP VIEW)
• BiCMOS Process With TTL Inputs and
Outputs
• BiCMOS Design Reduces Standby Current
OEA
A1
V
CC
B1
1
24
23
22
21
20
19
18
17
16
15
14
• Flow-Through Pinout (All Inputs on
2
Opposite Side From Outputs)
A2
B2
3
A3
B3
4
• Functionally Equivalent to SN74ALS29834
A4
B4
5
and AMD Am29834
A5
B5
6
• High-Speed Bus Transceiver With Parity
A6
B6
7
Generator/Checker
A7
B7
8
• Parity-Error Flag With Open-Collector
A8
B8
9
Output
ERR
CLR
PARITY
OEB
10
11
• Available Register For Storage of the
Parity-Error Flag
GND 12
13 CLK
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
description
The SN74BCT29834 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between
data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted
from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not
an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device
so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with an open-collector parity-error flag (ERR). ERR is clocked into the register on the rising edge of the CLK
input. The error flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are
low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced
error condition which gives the designer more system diagnostic capability. The SN74BCT29834 provides
inverting logic.
The SN74BCT29834 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
CLK
OUTPUT AND I/O
†
Bi
∑ of L’s
FUNCTION
Ai
∑ of H’s
‡
A
B
PARITY
ERR
OEB
OEA
CLR
Odd
Even
H
L
L
H
X
X
NA
NA
A
NA
A data to B bus and generate parity
Odd
Even
H
L
H
X
L
H
L
↑
NA
B
X
NA
NA
NA
NA
B data to A bus and check parity
Clear error-flag register
X
X
X
X
H
H
L
H
H
No↑
No↑
↑
X
X
Odd
Even
NC
H
L
§
Isolation
H
L
H
L
X
Z
Z
A
Z
↑
H
Odd
Even
L
H
A data to B bus and generate inverted
parity
X
X
NA
NA
NA
NA = not applicable, NC = no change, X = don’t care
†
‡
§
Summation of high-level inputs includes PARITY along with Bi inputs.
Output states shown assume the ERR output was previously high.
In this mode, the ERR output, when enabled, shows inverted parity of the A bus.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT29834
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993
functional logic diagram (positive logic)
8x
8
8
A1–A8
B1–B8
EN
8
8x
EN
OEB
PARITY
8
OEA
8
MUX
1
1
2k
9
P
1
1
G1
1D
ERR
CLK
CLR
C1
R
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT29834
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993
error-flag waveforms
H
L
OEB
H
L
OEA
Even
Odd
Bi + PARITY
t
su
t
h
H
L
CLK
t
t
w
su
t
w
H
L
CLR
ERR
t
t
PLH
PHL
H
L
ERROR-FLAG FUNCTION TABLE
INTERNAL
TO DEVICE
OUTPUT
PRESTATE
INPUTS
OUTPUT
FUNCTION
†
POINT P
CLR
CLK
ERR
n–1
ERR
H
H
H
↑
↑
↑
H
X
L
H
L
X
H
L
L
Sample
Clear
L
X
X
X
H
†
ERR represents the state of the ERR output before any changes at CLR, CLK,
n–1
or point P.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Voltage applied to a disabled I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT29834
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
High-level input voltage
Low-level input voltage
High-level output voltage, ERR
High-level output current
Low-level output current
Operating free-air temperature
V
IH
0.8
2.4
–24
48
V
IL
V
OH
I
I
mA
mA
°C
OH
OL
T
A
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
= 4.5 V,
= 4.5 V
–1.2
V
IK
CC
I
I
= –15 mA
= –24 mA
2.4
2
OH
OH
V
All inputs/outputs except ERR
ERR
OH
CC
I
I
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
V
= 2.4 V
20
0.5
µA
V
OH
OH
= 48 mA
V
OL
I
0.35
OL
V = 5.5 V
I
I
0.1
mA
µA
I
I
‡
V = 2.7 V
I
20
IH
Data
–0.2
–0.75
–250
80
‡
V
= 5.5 V,
V = 0.4 V
I
mA
I
CC
IL
Control
§
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 0
O
–75
mA
mA
mA
OS
Outputs open
Outputs open
55
30
CCL
45
CCZ
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
These parameters include off-state output current for I/O ports only.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
MIN
10
10
10
12
12
0
MAX
UNIT
CLK high
t
Pulse duration
CLK low
ns
w
CLR low
Bi and PARITY
CLR inactive
Bi and PARITY
t
t
ns
ns
Setup time before CLK↑
Hold time after CLK↑
su
h
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT29834
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Note 1)
L
V
= 5 V,
V
= 4.5 V to 5.5 V,
C = 50 pF,
L
CC
CC
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
R1 = 500 Ω,
R2 = 500 Ω,
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
T = MIN to MAX
A
T
= 25°C
TYP
5
A
MIN
1
MAX
7
MIN
1
MAX
8
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
A or B
A
B or A
PARITY
A or B
ns
ns
ns
ns
ns
ns
1.5
1.5
1.5
2
4
6
1.5
1.5
1.5
2
7
10
8
13
10
15
19
11
17
10
17
13
13
15
15
19
21
15
21
12
18
15
15
11
15
8
OEA or OEB
OEA or OEB
2
2
2
2
A or B
2
13
7
2
CLK
CLR
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
t
ERR
PLH
13
10
10
t
t
PLH
PARITY
OEA
PHL
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 1: Load circuits and voltage waveforms are shown in Section 1.
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–6
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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