SN74BCT533N [TI]
Octal D-Type Transparent Latches 20-PDIP 0 to 70;
| 型号： | SN74BCT533N |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Octal D-Type Transparent Latches 20-PDIP 0 to 70 驱动 信息通信管理 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74BCT533
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS055A – JULY 1990 – REVISED NOVEMBER 1993
DW OR N PACKAGE
(TOP VIEW)
• State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
• Full Parallel Access for Loading
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
• 3-State Inverting Outputs Drive Bus Lines
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
or Buffer Memory Address Registers
• ESD Protection Exceeds 2000 V
Per MIL-Std-883C, Method 3015
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (N)
description
GND
The SN74BCT533 is an 8-bit transparent D-type
latch with 3-state outputs designed specifically for
driving highly capacitive or relatively low-imped-
ance loads. It is particularly suitable for
implementing buffer registers, I/O ports, bidirec-
tional bus drivers, and working registers.
When the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When
LE is taken low, the Q outputs are latched at the inverse of the levels set up at the D inputs. The SN74BCT533
provides inverted data at its outputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
The output-enable (OE) input does not affect the internal operations of the latch. Previously stored data can be
retained or new data can be entered while the outputs are in the high-impedance state.
The SN74BCT533 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
L
L
H
L
X
X
Q
0
H
X
Z
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT533
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS055A – JULY 1990 – REVISED NOVEMBER 1993
†
logic symbol
logic diagram (positive logic)
1
OE
1
EN
C1
OE
LE
11
11
LE
2
5
C1
1Q
2Q
3
2
5
3
1D
2D
3D
4D
5D
6D
7D
8D
1D
1
1Q
2Q
1D
1D
4
7
6
3Q
4Q
5Q
6Q
C1
1D
8
9
4
7
13
14
17
18
12
15
16
19
2D
3D
6
9
C1
1D
3Q
4Q
5Q
6Q
7Q
7Q
8Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
C1
1D
8
4D
5D
6D
12
15
16
C1
1D
13
14
C1
1D
C1
1D
17
18
7D
8D
19
C1
1D
8Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT533
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS055A – JULY 1990 – REVISED NOVEMBER 1993
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
I
Voltage range applied to any output in the disabled or power-off state, V . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
O
Voltage range applied to any output in the high state, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V
O
CC
Input clamp current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
V
0.8
–18
–15
64
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
T
A
0
70
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT533
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS055A – JULY 1990 – REVISED NOVEMBER 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
= 4.5 V,
= 4.5 V
–1.2
V
IK
CC
I
I
I
I
I
= –3 mA
= –15 mA
= –3 mA
= 64 mA
2.4
2
3.3
3.1
OH
OH
OH
OL
CC
V
OH
OL
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.75 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V
= 5.5 V
= 5.5 V
= 5 V,
2.7
0.42
0.55
0.4
20
V
I
I
I
I
I
I
I
I
I
V = 5.5 V
I
mA
µA
mA
mA
µA
µA
mA
mA
mA
pF
I
V = 2.7 V
I
IH
IL
V = 0.5 V
I
–0.6
–225
50
‡
V
O
V
O
V
O
= 0
–100
OS
= 2.7 V
= 0.5 V
OZH
OZL
CCL
CCH
CCZ
–50
63
40
5
8
5
8
C
C
V = 2.5 V or 0.5 V
I
6
i
= 5 V,
V
O
= 2.5 V or 0.5 V
11
pF
o
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
MIN
MAX
UNIT
MIN
4
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
4
2.5
3
ns
ns
ns
High or low
High or low
2.5
3
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT533
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS055A – JULY 1990 – REVISED NOVEMBER 1993
switching characteristics (see Note 2)
V
= 5 V,
= 50 pF,
= 500 Ω,
= 500 Ω,
= 25°C
V
= 4.5 V to 5.5 V,
= 50 pF,
CC
CC
C
R
R
C
R
R
L
1
2
L
1
2
= 500 Ω,
FROM
PARAMETER
TO
(OUTPUT)
UNIT
(INPUT)
= 500 Ω,
†
T = MIN to MAX
A
T
A
MIN
2.8
2.7
2.3
2.5
3.1
3.7
1.8
1.3
TYP
6.1
5.3
5
MAX
9.1
8.2
7.7
7.6
8.8
10
MIN
2.8
2.7
2.3
2.5
3.1
3.7
1.8
1.3
MAX
11.2
9.3
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
ns
ns
ns
ns
Q
Q
Q
Q
8.6
LE
4.9
6.1
6.9
3.9
3.5
8.1
10.8
12
OE
OE
5.9
6.1
6.9
7.2
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
PDIP
Drawing
SN74BCT533DW
SN74BCT533DWR
SN74BCT533N
OBSOLETE
OBSOLETE
OBSOLETE
DW
20
20
20
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
DW
N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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