SN74BCT899DWR [TI]
9-BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER;
| 型号： | SN74BCT899DWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 9-BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER |
| 文件： | 总8页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74BCT899
9-BIT LATCHABLE TRANSCEIVER
WITH PARITY GENERATOR/CHECKER
SCBS253 – JUNE 1992 – REVISED NOVEMBER 1993
DW PACKAGE
(TOP VIEW)
• State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ODD/EVEN
ERRA
LEAB
A1
V
CC
OEAB
2
3
B1
B2
B3
B4
B5
B6
B7
B8
BPAR
LEBA
SEL
ERRB
4
• Option to Select Generate Parity and Check
or Feed-Through Data/Parity in A-to-B or
B-to-A Directions
5
A2
A3
A4
A5
A6
A7
A8
6
7
• Simultaneously Generates and Checks
8
Parity
9
• Packaged in Plastic Small-Outline Package
10
11
12
13
14
description
APAR
OEBA
GND
The SN74BCT899 is a 9-bit to 9-bit parity
transceiver with transparent latches. The device
can operate as a feed-through transceiver or it can
generate/check parity from the 8-bit data buses in
either direction. It has a current-sinking capability
of 24 mA at the A bus and 64 mA at the B bus.
The SN74BCT899 features independent latch-
enable (LEAB or LEBA) inputs, a select (SEL)
input for ODD/EVEN parity, and separate
error-signal(ERRAorERRB)outputsforchecking
parity.
The SN74BCT899 is characterized for operation
from 0°C to 70°C.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT899
9-BIT LATCHABLE TRANSCEIVER
WITH PARITY GENERATOR/CHECKER
SCBS253 – JUNE 1992 – REVISED NOVEMBER 1993
FUNCTION TABLE
OPERATION OR FUNCTION
INPUTS
OEAB OEBA
SEL LEAB LEBA
H
H
X
X
X
Buses A and B are in the high-impedance state.
Generates parity from B1–B8 based on ODD/EVEN. Generated parity → APAR. Generated parity
checked against BPAR and output as ERRB.
H
L
L
X
H
Generates parity from B1–B8 based on ODD/EVEN. Generated parity → APAR. Generated parity
checked against BPAR and output as ERRB. Generated parity also fed back through the A latch
for generate/check as ERRA.
H
L
L
H
H
Generates parity from B-latch data based on ODD/EVEN. Generated parity → APAR. Generated
parity checked against latched BPAR and output as ERRB.
H
H
H
L
L
L
L
H
H
L
X
X
H
H
L
H
H
X
BPAR/B1–B8 → APAR/A1–A8 feed-through mode. Generated parity checked against BPAR and
output as ERRB.
BPAR/B1–B8 → APAR/A1–A8 feed-through mode. Generated parity checked against BPAR and
output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA.
L
Generates parity from A1–A8 based on ODD/EVEN. Generated parity → BPAR. Generated parity
checked against APAR and output as ERRA.
H
Generates parity from A1–A8 based on ODD/EVEN. Generated parity → BPAR. Generated parity
checked against APAR and output as ERRA. Generated parity also fed back through the B latch
for generate/check as ERRB.
L
H
L
H
H
Generates parity from A-latch data based on ODD/EVEN. Generated parity → BPAR. Generated
parity checked against latched APAR and output as ERRA.
L
L
H
H
L
L
X
X
APAR/A1–A8 → BPAR/B1–B8 feed-through mode. Generated parity checked against APAR and
output as ERRA.
H
H
APAR/A1–A8 → BPAR/B1–B8 feed-through mode. Generated parity checked against APAR and
output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB.
L
L
H
L
H
X
H
X
X
X
Output to A bus and B bus
PARITY FUNCTION TABLE
†
INPUTS
OUTPUTS
Σ OF INPUTS
A1–A8 = H
‡
ODD/EVEN
APAR BPAR
ERRA
L
L
0, 2, 4, 6, 8
1, 3, 5, 7
L
L
L
H
L
H
L
L
0, 2, 4, 6, 8
1, 3, 5, 7
H
H
L
L
L
H
H
L
H
L
H
H
H
H
0, 2, 4, 6, 8
1, 3, 5, 7
L
H
H
L
0, 2, 4, 6, 8
1, 3, 5, 7
H
H
H
L
†
If LE = H, current A1–A8 and APAR data is used. If LE = L,
latched A1–A8 and APAR data is used.
ThisisthevalueofBPARifSEL=L. IfSEL=H, BPAR=APAR.
‡
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT899
9-BIT LATCHABLE TRANSCEIVER
WITH PARITY GENERATOR/CHECKER
SCBS253 – JUNE 1992 – REVISED NOVEMBER 1993
logic diagram (positive logic)
ODD/EVEN
SEL
OEBA
LEAB
OEAB
LEBA
9-Bit
Transp.
Latch
9-Bit
Buffer
A1
A2
B1
B2
A3
B3
A4
B4
Parity
Generator
A5
B5
A6
B6
A7
B7
A8
B8
APAR
BPAR
ERRA
ERRB
Parity
Generator
9-Bit
Transp.
Latch
9-Bit
Buffer
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the disabled or power-off state, V . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Voltage range applied to any output in the high state, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
IK
I
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
O
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT899
9-BIT LATCHABLE TRANSCEIVER
WITH PARITY GENERATOR/CHECKER
SCBS253 – JUNE 1992 – REVISED NOVEMBER 1993
recommended operating conditions (see Note 2)
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
V
V
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
0.8
0
V
CC
–3
A1–A8
I
High-level output current
Low-level output current
mA
mA
OH
OL
B1–B8
–15
24
64
10
70
A1–A8
I
B1–B8
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
Outputs enabled
ns/V
T
A
0
°C
NOTE 2: Unused or floating pins (input or I/O) must be held high or low.
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT899
9-BIT LATCHABLE TRANSCEIVER
WITH PARITY GENERATOR/CHECKER
SCBS253 – JUNE 1992 – REVISED NOVEMBER 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
= 4.5 V,
I = –18 mA
–1.2
V
IK
CC
I
= 4.75 V,
I
I
I
I
I
I
I
I
I
I
I
= –1 mA
= –1 mA
= –3 mA
= –3 mA
= –3 mA
= –12 mA
= –15 mA
= 20 mA
= 24 mA
= 48 mA
= 64 mA
2.7
2.5
2.4
2.7
2.4
3.4
3.4
3.3
3.4
3.4
CC
OH
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
A1–A8, APAR, ERRA, ERRB
V
= 4.5 V
CC
CC
V
OH
V
= 4.75 V,
V
B1–B8, BPAR
V
CC
= 4.5 V
= 4.5 V
2
3.1
0.35
0.42
A1–A8, APAR, ERRA, ERRB
B1–B8, BPAR
0.5
V
OL
V
CC
V
0.55
100
20
‡
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 5.5 V
I
µA
µA
µA
I
‡
V = 2.7 V
I
IH
‡
V = 0.5 V
I
–20
–150
–225
2
IL
A1–A8, APAR, ERRA, ERRB
B1–B8, BPAR
–60
§
V
CC
= 5.5 V,
V
O
= 0
mA
I
OS
–100
A to B
B to A
A to B
B to A
A to B
B to A
A to B
B to A
0.5
0.5
43
Outputs high
2
69
Outputs low
22
34
I
V
CC
= 5.5 V,
Outputs open
mA
CC
6
10
Outputs disabled, ERR outputs low
Outputs disabled, ERR outputs high
6
10
0.5
0.5
6.5
10.5
12.5
2
2
C
C
V
V
= 5 V,
= 5 V,
V = 0.5 V
I
pF
pF
i
CC
A ports
B ports
V
O
= 0.5 V
io
CC
†
‡
§
All typical values are at V
For I/O ports, the parameters I and I include the off-state output current.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
= 5 V, T = 25°C.
A
IH IL
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
MIN
MAX
UNIT
MIN
5
MAX
t
w
t
su
t
h
Pulse duration
5
4.5
1.5
ns
ns
ns
Setup time before LE↓
Hold time after LE↓
Data high or low
Data high or low
4.5
1.5
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT899
9-BIT LATCHABLE TRANSCEIVER
WITH PARITY GENERATOR/CHECKER
SCBS253 – JUNE 1992 – REVISED NOVEMBER 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Note 3)
L
V
T
= 5 V,
= 25°C
CC
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MIN
1.9
1.8
4.3
4.5
2.2
1.7
3.4
3.6
4.6
4.1
4.5
4.4
1.4
1.6
2.6
3.3
3
TYP
6
MAX
7.6
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1.9
1.8
4.3
4.5
2.2
1.7
3.4
3.6
4.6
4.1
4.5
4.4
1.4
1.6
2.6
3.3
3
9.1
8.1
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
A or B
A or B
B or A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.2
11
6.8
13
16.1
15.3
8
BPAR or APAR
BPAR or APAR
10.7
5.2
4.7
10.6
10.5
8.8
8.4
9
12.7
6.7
APAR or BPAR
6.3
7.6
12.6
12.5
10.5
10.2
10.7
10.7
6.2
15.7
15.3
12.8
12.8
13.1
13.3
7.7
A, APAR, or
B, BPAR
ERRA or ERRB
ERRA or ERRB
BPAR or APAR
BPAR or APAR
B or A
ODD/EVEN
ODD/EVEN
8.5
4.6
4.4
7.6
6.5
6.7
6.1
10.2
8.9
10.3
9.2
5.6
10.5
6.4
5.5
SEL
5.9
7.1
9.3
10.9
9.3
LEAB OR LEBA
LEAB OR LEBA
LEAB OR LEBA
LEAB OR LEBA
8.2
8.3
9.9
BPAR or APAR
(parity feed-through)
3
7.7
3
8.7
5.2
5.1
5.3
5
12.1
10.7
12.3
11
5.2
5.1
5.3
5
14.8
12.5
14.9
12.9
9
BPAR or APAR
(parity generated)
ERRB or ERRA
B or A
1.8
2.1
2.9
2.1
7.2
1.8
2.1
2.9
2.1
OEAB or OEBA
OEAB or OEBA
12.2
8.1
13.9
9.8
B or A
7.1
8.1
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
SOIC
Drawing
SN74BCT899DW
SN74BCT899DWR
SN74BCT899DWR
OBSOLETE
OBSOLETE
OBSOLETE
DW
28
28
28
TBD
TBD
TBD
Call TI
Call TI
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DW
DW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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