SN74CB3Q3257_15 [TI]
FET Multiplexer/Demultiplexer;
| 型号： | SN74CB3Q3257_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FET Multiplexer/Demultiplexer |
| 文件： | 总13页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCDS135A – SEPTEMBER 2003 − REVISED NOVEMBER 2003
D
D
D
High-Bandwidth Data Path
(Up to 500 MHz )
D
D
Data and Control Inputs Provide
Undershoot Clamp Diodes
†
5-V Tolerant I/Os with Device Powered-Up
or Powered-Down
Low Power Consumption
(I
= 0.7 mA Typical)
CC
Low and Flat ON-State Resistance (r
)
D
V
Operating Range From 2.3 V to 3.6 V
on
CC
Characteristics Over Operating Range
(r = 4 Ω Typical)
D
Data I/Os Support 0- to 5-V Signaling
Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V,
5 V)
on
D
Rail-to-Rail Switching on Data I/O Ports
− 0- to 5-V Switching With 3.3-V V
− 0- to 3.3-V Switching With 2.5-V V
CC
CC
D
D
D
D
Control Inputs Can be Driven by TTL or
5-V/3.3-V CMOS Outputs
D
D
Bidirectional Data Flow, With Near-Zero
Propagation Delay
I
Supports Partial-Power-Down Mode
off
Operation
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
(C
= 3.5 pF Typical)
io(OFF)
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
D
Fast Switching Frequency (f
Max)
= 20 MHz
OE
†
For additional information regarding the performance
characteristics of the CB3Q family, refer to the TI
application report, CBT-C, CB3T, and CB3Q
Signal-Switch Families, literature number SCDA008.
− 1000-V Charged-Device Model (C101)
D
Supports Both Digital and Analog
Applications: USB Interface, Differential
Signal Interface, Bus Isolation,
Low-Distortion Signal Gating
DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
V
1
2
3
4
5
6
7
8
16
S
1B1
1B2
1A
2B1
2B2
2A
CC
15 OE
14 4B1
13 4B2
12 4A
1
16
1B1
1B2
1A
2B1
2B2
2A
15
14
13
12
11
10
2
3
4
5
6
7
OE
4B1
4B2
4A
3B1
3B2
11
10
9
3B1
3B2
3A
GND
8
9
description/ordering information
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
QFN − RGY
Tape and reel SN74CB3Q3257RGYR
BU257
SSOP (QSOP) − DBQ Tape and reel SN74CB3Q3257DBQR
BU257
−40°C to 85°C
TSSOP − PW
TVSOP − DGV
Tape and reel SN74CB3Q3257PWR
Tape and reel SN74CB3Q3257DGVR
BU257
BU257
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢈꢙ ꢉꢊꢚ ꢗꢆ ꢙ ꢆ ꢊꢚ ꢓ ꢎꢛꢊꢚ ꢎꢓꢌꢜꢝ ꢐ ꢞ ꢟꢋ ꢝ ꢟꢊꢅ ꢜꢁꢘꢛ ꢋ ꢘꢌ ꢟ ꢅꢒꢀ ꢀꢛ ꢋ ꢌꢄ ꢟ
SCDS135A – SEPTEMBER 2003 − REVISED NOVEMBER 2003
description/ordering information (continued)
The SN74CB3Q3257 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage
of the pass transistor, providing a low and flat ON-state resistance (r ). The low and flat ON-state resistance
on
allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The
device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data
bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3257 provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
The SN74CB3Q3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer with a single output-enable
(OE) input. The select (S) input controls the data path of the multiplexer/demultiplexer. When OE is low, the
multiplexer/demultiplexer is enabled and the A port is connected to the B port, allowing bidirectional data flow
between ports. When OE is high, the multiplexer/demultiplexer is disabled and a high-impedance state exists
between the A and B ports.
This device is fully specified for partial-power-down applications using I . The I circuitry prevents damaging
off
off
current backflow through the device when it is powered-down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
INPUT/OUTPUT
A
FUNCTION
OE
S
L
L
L
B1
B2
Z
A port = B1 port
A port = B2 port
Disconnect
H
X
H
2
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SCDS135A – SEPTEMBER 2003 − REVISED NOVEMBER 2003
logic diagram (positive logic)
4
2
1A
1B1
SW
3
SW
SW
1B2
2B1
7
5
6
2A
SW
SW
SW
2B2
9
11
10
3A
3B1
3B2
SW
SW
12
14
13
4A
4B1
4B2
1
S
15
OE
simplified schematic, each FET switch (SW)
A
B
V
CC
Charge
Pump
†
EN
†
EN is the internal enable signal applied to the switch.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS135A – SEPTEMBER 2003 − REVISED NOVEMBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IN
I/O
IK IN
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/OK I/O
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Continuous current through V
IO
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
I/O
.
I
O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
MIN
2.3
1.7
2
MAX
3.6
5.5
5.5
0.7
0.8
5.5
85
UNIT
V
V
Supply voltage
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
High-level control input voltage
V
V
IH
0
V
V
Low-level control input voltage
IL
0
Data input/output voltage
0
V
I/O
T
A
Operating free-air temperature
−40
°C
NOTE 7: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS135A – SEPTEMBER 2003 − REVISED NOVEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
−1.8
1
UNIT
V
V
IK
V
V
= 3.6 V,
= 3.6 V,
I = −18 mA
CC
I
I
I
I
I
Control inputs
V
= 0 to 5.5 V
µA
IN
CC
IN
V
= 0 to 5.5 V,
Switch OFF,
O
‡
V
V
V
= 3.6 V,
= 0,
1
1
µA
µA
mA
µA
OZ
CC
CC
CC
V = 0,
I
V
= V
or GND
IN
V = 0
CC
V
O
= 0 to 5.5 V,
= 0,
off
I
I
I/O
= 3.6 V,
V
IN
= V
or GND
0.7
1.5
30
CC
CC
Switch ON or OFF,
§
¶
∆I
CC
Control inputs
V
V
= 3.6 V,
One input at 3 V,
Other inputs at V or GND
CC
CC
Per control
input
= 3.6 V, A and B ports open,
Control input switching at 50% duty cycle
mA/
MHz
CC
I
0.3
2.5
5.5
0.35
3.5
7
CCD
C
Control inputs
A port
V
= 3.3 V,
= 3.3 V,
V
= 5.5 V, 3.3 V, or 0
pF
pF
in
CC
CC
IN
Switch OFF,
= V or GND,
V
V
V
= 5.5 V, 3.3 V, or 0
= 5.5 V, 3.3 V, or 0
I/O
V
IN
CC
Switch OFF,
= V
C
io(OFF)
B port
V
CC
= 3.3 V,
3.5
5
pF
pF
I/O
V
or GND,
or GND,
IN
CC
Switch ON,
= V
A port
B port
10.5
10.5
4
13
13
8
C
V
V
= 3.3 V,
= 2.3 V,
V
I/O
= 5.5 V, 3.3 V, or 0
io(ON)
#
CC
V
IN
CC
V = 0,
I
I
O
I
O
I
O
I
O
= 30 mA
CC
TYP at V
CC
= 2.5 V
V = 1.7 V,
I
= −15 mA
= 30 mA
= −15 mA
4
9
Ω
r
on
V = 0,
I
4
6
V
CC
= 3 V
V = 2.4 V,
I
4
8
V
†
‡
§
¶
#
and I refer to control inputs. V , V , I , and I refer to data pins.
IN
IN
I
O
I
O
All typical values are at V
= 3.3 V (unless otherwise noted), T = 25°C.
CC
A
For I/O ports, the parameter I
includes the input leakage current.
OZ
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 2).
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
V
= 2.5 V
V
= 3.3 V
CC
0.2 V
CC
0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
||
f
t
t
or f
OE or S
A or B
B or A
A
10
0.12
6.5
6.5
6.5
6
20
0.2
5.5
5.5
5.5
6
MHz
ns
OE
S
k
A or B
S
pd
1.5
1.5
1.5
1
1.5
1.5
1.5
1
ns
pd(s)
B
S
t
t
ns
ns
en
A or B
B
OE
S
dis
A or B
1
6
1
6
OE
||
k
Maximum switching frequency for control inputs (V > V , V = 5 V, R ≥ 1 MΩ, C = 0).
CC
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
O
I
L
L
5
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ꢋ
ꢌꢄ
ꢟ
SCDS135A – SEPTEMBER 2003 − REVISED NOVEMBER 2003
TYPICAL r
vs
on
V
I
16
V
= 3.3 V
= 25°C ,
= −15 mA
CC
14
12
10
8
T
A
O
I
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
V − V
3.0
3.5
4.0
4.5
5.0
I
Figure 1. Typical r vs V , V
= 3.3 V and I = −15 mA
O
on
I
CC
TYPICAL I
vs
CC
CONTROL-INPUT SWITCHING FREQUENCY
12
10
8
V
= 3.3 V
CC
= 25°C
T
A
A and B Ports Open
6
S Switching
OE Switching
4
2
0
0
2
4
6
8
10
12
14
16
18
20
OE or S Switching Frequency − MHz
Figure 2. Typical I
vs OE or S Switching Frequency, V
= 3.3 V
CC
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢆ ꢈꢉꢂ
ꢃ ꢊꢅꢋ ꢌ ꢍ ꢊꢎ ꢏꢊ ꢈ ꢏ ꢐꢌ ꢑ ꢒꢓꢌ ꢋꢔ ꢓꢐ ꢕꢐꢖꢗ ꢘꢐꢑ ꢒꢓꢌꢋ ꢔ ꢓꢐ ꢕꢐ ꢖ
ꢈ ꢙ ꢉ ꢊꢚ ꢗꢆ ꢙꢆ ꢊꢚ ꢓ ꢎꢛꢊꢚꢎ ꢓꢌꢜꢝ ꢐꢞ ꢟꢋ ꢝꢟ ꢊꢅꢜꢁꢘꢛ ꢋ ꢘꢌ ꢟ ꢅꢒ ꢀ ꢀ ꢛꢋ ꢌꢄ ꢟ
SCDS135A – SEPTEMBER 2003 − REVISED NOVEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
CC
Open
Input Generator
50 Ω
S1
R
V
V
O
L
I
GND
50 Ω
V
G2
C
R
L
L
(see Note A)
S1
V
I
V
∆
C
R
V
CC
TEST
L
L
2.5 V 0.2 V
3.3 V 0.3 V
Open
Open
500 Ω
500 Ω
V
CC
V
CC
or GND
or GND
30 pF
50 pF
t
pd(s)
2.5 V 0.2 V
3.3 V 0.3 V
2 × V
2 × V
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
CC
CC
t
/t
PLZ PZL
2.5 V 0.2 V
3.3 V 0.3 V
GND
GND
500 Ω
500 Ω
V
CC
V
CC
30 pF
50 pF
0.15 V
0.3 V
t
/t
PHZ PZH
Output
Control
(V
V
CC
V
CC
/2
V
CC
/2
)
IN
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
Output
Control
V
CC
V
/2
CC
S1 at 2 × V
(see Note B)
V
V
+ V
V
CC
/2
V
CC
/2
CC
OL
∆
(V
IN
)
OL
0 V
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
OH
− V
OH
∆
V
/2
Output
CC
V
CC
/2
V
CC
/2
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
are the same as t
en
. The t propagation delay is the calculated RC time constant of the typical ON-state resistance
pd
pd(s)
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
SN74CB3Q3257DBQR
SN74CB3Q3257DGVR
SN74CB3Q3257PW
SN74CB3Q3257PWR
SN74CB3Q3257RGYR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
16
16
16
16
16
2500
2000
90
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
TVSOP
TSSOP
TSSOP
QFN
DGV
PW
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
Pb-Free
(RoHS)
PW
2000
Pb-Free
(RoHS)
RGY
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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