SN74CB3T16212DGVRE4 [TI]
IC,BUS EXCHANGER,CMOS,TSSOP,56PIN,PLASTIC;
| 型号： | SN74CB3T16212DGVRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,BUS EXCHANGER,CMOS,TSSOP,56PIN,PLASTIC 光电二极管 |
| 文件： | 总13页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A–OCTOBER 2003–REVISED FEBRUARY 2005
FEATURES
DGG OR DGV PACKAGE
•
Member of the Texas Instruments Widebus™
(TOP VIEW)
Family
•
•
Output Voltage Translation Tracks VCC
S0
1A1
1A2
2A1
2A2
3A1
3A2
GND
4A1
4A2
1
2
3
4
5
6
7
8
9
10
56 S1
55 S2
54
Supports Mixed-Mode Signal Operation on All
Data I/O Ports
1B1
53 1B2
52 2B1
51 2B2
50 3B1
– 5-V Input Down to 3.3-V Output Level Shift
With 3.3-V VCC
– 5-V/3.3-V Input Down to 2.5-V Output Level
Shift With 2.5-V VCC
49
48
47
GND
3B2
4B1
•
•
•
•
•
5-V-Tolerant I/Os With Device Powered Up or
Powered Down
Bidirectional Data Flow, With Near-Zero
Propagation Delay
5A1 11
5A2 12
6A1 13
46 4B2
45 5B1
44 5B2
Low ON-State Resistance (ron) Characteristics
(ron = 5 Ω Typ)
14
15
16
17
43
42
41
40
6A2
7A1
7A2
6B1
6B2
7B1
7B2
Low Input/Output Capacitance Minimizes
Loading (Cio(OFF) = 9 pF Typ)
V
CC
Data and Control Inputs Provide Undershoot
Clamp Diodes
8A1 18
39 8B1
19
20
21
22
23
24
25
26
27
28
38
37
36
35
34
33
32
31
30
29
GND
8A2
9A1
GND
8B2
9B1
•
•
•
Low Power Consumption (ICC = 70 µA Max)
VCC Operating Range From 2.3 V to 3.6 V
Data I/Os Support 0-V to 5-V Signaling Levels
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
9A2
9B2
10A1
10A2
11A1
11A2
12A1
12A2
10B1
10B2
11B1
11B2
12B1
12B2
•
•
•
•
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
•
•
Supports Digital Applications: Level
Translation, PCI Interface, USB Interface,
Memory Interleaving, and Bus Isolation
Ideal for Low-Power Portable Equipment
DESCRIPTION/ORDERING INFORMATION
The SN74CB3T16212 is a high-speed TTL-compatible FET bus-exchange switch, with low ON-state resistance
(ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data
I/O ports by providing voltage translation that tracks VCC. The SN74CB3T16212 supports systems using 5-V TTL,
3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A–OCTOBER 2003–REVISED FEBRUARY 2005
V
CC
5.5 V
V
CC
9 V
CC
IN
OUT
9 V − 1 V
CC
9 V − 1 V
CC
CB3T
0 V
0 V
Input Voltages
Output Voltages
NOTE: If the input high-voltage (V ) level is greater than or equal to V − 1 V and less than or equal to 5.5 V, the
IH
CC
output high-voltage (V ) level is equal to approximately the V voltage level.
OH
CC
Figure 1. Typical DC Voltage Translation Characteristics
The SN74CB3T16212 operates as a 24-bit bus switch or as a 12-bit bus exchange that provides data
exchanging between four signal ports. The select (S0, S1, S2) inputs control the data path of the bus-exchange
switch. When the bus-exchange switch is ON, the A port is connected to the B port, allowing bidirectional data
flow between ports. When the bus-exchange switch is OFF, a high-impedance state exists between the A and B
ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging
current will not backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, each select input should be tied to GND
through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of
the driver.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74CB3T16212DGGR
SN74CB3T16212DGVR
TOP-SIDE MARKING
CB3T16212
TSSOP – DGG
TVSOP – DGV
VFBGA – GQL
Tape and reel
Tape and reel
Tape and reel
KR212
–40°C to 85°C
SN74CB3T16212GQLR
KR212
VFBGA – ZQL (Pb-free) Tape and reel
SN74CB3T16212ZQLR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
2
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A–OCTOBER 2003–REVISED FEBRUARY 2005
GQL OR ZQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
TERMINAL ASSIGNMENTS
1
2
3
4
5
6
A
B
C
D
E
F
1A2
3A1
4A1
5A2
6A2
7A1
VCC
8A2
10A1
11A2
1A1
2A2
GND
4A2
6A1
7A2
GND
9A1
10A2
12A1
S0
S1
S2
1B1
2B2
3B2
5B1
6B1
6B2
7B2
8B2
10B1
11B2
2A1
3A2
5A1
1B2
3B1
4B2
2B1
GND
4B1
5B2
7B1
GND
9B1
10B2
12B1
G
H
J
8A1
9A2
8B1
9B2
11A1
12A2
11B1
12B2
K
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
FUNCTION
S2
L
S1
L
S0
L
A1
A2
Z
Z
Disconnect
L
L
H
L
B1 port
Z
Z
A1 port = B1 port
A1 port = B2 port
A2 port = B1 port
A2 port = B2 port
Disconnect
L
H
H
L
B2 port
L
H
L
Z
Z
Z
B1 port
B2 port
Z
H
H
L
H
A1 port = B1 port
A2 port = B2 port
H
H
H
H
L
B1 port
B2 port
B2 port
B1 port
A1 port = B2 port
A2 port = B1 port
H
3
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A–OCTOBER 2003–REVISED FEBRUARY 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
2
54
1A1
1B1
SW
SW
SW
3
53
30
SW
1B2
1A2
27
12A1
12B1
SW
SW
SW
28
29
SW
12B2
12A2
1
S0
S1
S2
56
55
4
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A–OCTOBER 2003–REVISED FEBRUARY 2005
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
A
B
V
G
(see Note A)
Control
Circuit
EN
(see Note B)
A. Gate voltage (VG) is equal to approximately VCC + VT when the switch is ON and VI > VCC + VT.
B. EN is the internal enable signal applied to the switch.
ABSOLUTE MAXIMUM RATINGS(1)
over free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
7
UNIT
V
VCC
VIN
VI/O
IIK
Supply voltage range(2)
Control input voltage range(2)(3)
Switch I/O voltage range(2)(3)(4)
Control input clamp current
I/O port clamp current
7
V
7
V
VIN < 0
VI/O < 0
–50
–50
±128
±100
64
mA
mA
mA
mA
II/OK
II/O
ON-state switch current(5)
Continuous current through VCC or GND
DGG package
θJA
Package thermal impedance(6)
DGV package
48
°C/W
°C
GQL/ZQL package
42
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output volrage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VI and VO are used to denote specific conditions for VI/O
(5) II and IO are used to denote specific conditions for II/O
.
.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
2.3
1.7
2
MAX
3.6
5.5
5.5
0.7
0.8
5.5
85
UNIT
VCC
VIH
Supply voltage
V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
High-level control input voltage
V
V
0
VIL
Low-level control input voltage
0
VI/O
TA
Data input/output voltage
0
V
Operating free-air temperature
–40
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A–OCTOBER 2003–REVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS(1)
PARAMETER
VIK
VOH
TEST CONDITIONS
MIN TYP(2)
MAX
UNIT
VCC = 3 V, II = –18 mA
See Figures 3 and 4
–1.2
V
Control
inputs
IIN
VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND
±10
µA
µA
VI = VCC – 0.7 V to 5.5 V
VI = 0.7 V to VCC – 0.7 V
VI = 0 to 0.7 V
±20
–40
±5
II
VCC = 3.6 V, VIN = VCC or GND, Switch ON
(3)
IOZ
Ioff
VCC = 3.6 V, VI = 0, VIN = VCC or GND, VO = 0 to 5.5 V, Switch OFF
VCC = 0, VI = 0, VO = 0 to 5.5 V
±10
10
µA
µA
VI = VCC or GND
VI = 5.5 V
70
VCC = 3.6 V, VIN = VCC or GND, II/O = 0,
Switch ON or OFF
ICC
µA
µA
70
Control
inputs
(4)
∆ICC
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND
300
Control
inputs
Cin
VCC = 3.3 V, VIN = VCC or GND
4
pF
pF
Cio(OFF)
Cio(ON)
VCC = 3.3 V, VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF
9
8
VI/O = 5.5 V or 3.3 V
VCC = 3.3 V, VIN = VCC or GND, Switch ON
VI/O = GND
pF
23
5
IO = 24 mA
VCC = 2.3 V, TYP at VCC = 2.5 V, VI = 0
IO = 16 mA
9.5
9.5
8.5
8.5
5
(5)
rON
Ω
IO = 64 mA
5
VCC = 3 V, VI = 0
IO = 32 mA
5
(1) VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
(2) All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
(5) Measured by the voltage drop between A and B terminals at the indicated current throught the switch. ON-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted) (see Figure 2)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
(1)
tpd
A or B
B or A
0.15
0.25
ns
ns
ns
ns
tpd(s)
ten
S
S
S
A
B
B
1
1
1
15.5
15
1
1
1
11.5
12
tdis
12
10.5
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capaitance, when driven by an ideal voltage source (zero output impedance).
6
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A–OCTOBER 2003–REVISED FEBRUARY 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
V
G1
TEST CIRCUIT
DUT
2 × V
CC
Input Generator
S1
Open
GND
R
L
V
V
O
I
50 Ω
C
L
50 Ω
R
G2
(see Note A)
L
S1
V
I
C
L
V
∆
R
L
V
CC
TEST
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V or GND
5.5 V or GND
30 pF
50 pF
t
pd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × V
2 × V
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
CC
t
/t
PLZ PZL
CC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V
5.5 V
30 pF
50 pF
0.15 V
0.3 V
t
/t
PHZ PZH
Output
Control
V
CC
V /2
CC
V /2
CC
(V )
IN
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
Output
Control
(V
V
CC
V /2
CC
S1 at 2 × V
V + V
∆
OL
V /2
CC
V /2
CC
CC
)
(see Note B)
IN
OL
0 V
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
V
OH
− V
∆
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
en
are the same as t
. The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
pd(s)
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Test Circuit and Voltage Waveforms
7
SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS157A–OCTOBER 2003–REVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE vs INPUT VOLTAGE
= 2.3 V
= 1 µA
= 25°C
OUTPUT VOLTAGE vs INPUT VOLTAGE
V = 3 V
CC
4.0
3.0
2.0
1.0
0.0
4.0
3.0
2.0
1.0
0.0
V
CC
I
O
I
O
= 1 µA
T = 25°C
A
T
A
0.0
2.0
4.0
6.0
1.0
3.0
5.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 3. Data Output Voltage vs Data Input Voltage
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
4.0
3.5
4.0
3.5
3.0
2.5
2.0
1.5
V
= 2.3 V ~ 3.6 V
V
= 2.3 V ~ 3.6 V
CC
CC
V = 5.5 V
V = 5.5 V
I
I
100 µA
100 µA
T
A
= 85°C
T
A
= 25°C
8 mA
16 mA
24 mA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
V
= 2.3 V ~ 3.6 V
CC
V = 5.5 V
I
100 µA
T
A
= -40°C
8 mA
16 mA
24 mA
3.3
− Supply Voltage − V
2.3
2.5
2.7
2.9
3.1
3.5
3.7
V
CC
Figure 4. VOH Values
8
PACKAGE OPTION ADDENDUM
www.ti.com
12-May-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
74CB3T16212DGVRE4
SN74CB3T16212DGGR
ACTIVE
ACTIVE
TVSOP
TSSOP
DGV
56
56
2000
2000
TBD
Call TI
Call TI
DGG
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74CB3T16212DGVR
SN74CB3T16212ZQLR
ACTIVE
ACTIVE
TVSOP
VFBGA
DGV
ZQL
56
56
2000
1000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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