SN74CB3T3245DWRE4 [TI]
8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE BUS SWTCH WITH 5-V-TOLERANK LEVEL SHIFTER; 8位FET总线开关2.5 -V / 3.3 V低电压总线， 5 -V - TOLERANK电平转换器SWTCH
| 型号： | SN74CB3T3245DWRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE BUS SWTCH WITH 5-V-TOLERANK LEVEL SHIFTER |
| 文件： | 总14页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CB3T3245
8-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS136–OCTOBER 2003–REVISED MARCH 2005
FEATURES
•
•
VCC Operating Range From 2.3 V to 3.6 V
•
•
•
Standard '245-Type Pinout
Data I/Os Support 0- to 5-V Signaling Levels
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
Output Voltage Translation Tracks VCC
•
•
•
•
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Supports Mixed-Mode Signal Operation on All
Data I/O Ports
Ioff Supports Partial-Power-Down Mode
Operation
– 5-V Input Down to 3.3-V Output Level Shift
With 3.3-V VCC
Latch-Up Performance Exceeds 250 mA
Per JESD 17
– 5-V/3.3-V Input Down to 2.5-V Output Level
Shift With 2.5-V VCC
ESD Performance Tested Per JESD 22
•
•
•
•
•
•
5-V-Tolerant I/Os With Device Powered Up or
Powered Down
– 2000-V Human-Body Model (A114-B,
Class II)
Bidirectional Data Flow With Near-Zero
Propagation Delay
– 1000-V Charged-Device Model (C101)
Low ON-State Resistance (ron) Characteristics
(ron = 5 Ω Typ)
•
•
Supports Digital Applications: Level
Translation, PCI Interface, USB Interface,
Memory Interleaving, Bus Isolation
Low Input/Output Capacitance Minimizes
Loading (Cio(OFF) = 5 pF Typ)
Ideal for Low-Power Portable Equipment
Data and Control Inputs Provide Undershoot
Clamp Diodes
Low Power Consumption (ICC = 40 µA Max)
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
NC
A1
A2
A3
A4
A5
A6
A7
A8
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
NC − No internal connection
DESCRIPTION/ORDERING INFORMATION
The SN74CB3T3245 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing
for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by
providing voltage translation that tracks VCC. The SN74CB3T3245 supports systems using 5-V TTL, 3.3-V
LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74CB3T3245
8-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS136–OCTOBER 2003–REVISED MARCH 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
V
CC
5.5 V
V
CC
9 V
CC
IN
OUT
9 V − 1 V
CC
9 V − 1 V
CC
CB3T
0 V
0 V
Input Voltages
Output Voltages
NOTE A: If the input high-voltage (V ) level is greater than or equal to (V − 1 V) and less than or equal to 5.5 V,
IH
CC
then the output high-voltage (V ) level will be equal to approximately the V voltage level.
OH
CC
Figure 1. Typical DC Voltage Translation Characteristics
The SN74CB3T3245 is an 8-bit bus switch with a single ouput-enable (OE) input and a standard '245 pinout.
When OE is low, the 8-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data
flow between ports. When OE is high, the 8-bit bus switch is OFF, and a high-impedance state exists between
the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging
current will not backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE(1)
Tube
ORDERABLE PART NUMBER
SN74CB3T3245DW
TOP-SIDE MARKING
CB3T3245
SOIC – DW
Tape and reel
Tape and reel
Tube
SN74CB3T3245DWR
SN74CB3T3245DBQR
SN74CB3T3245PW
SN74CB3T3245PWR
SN74CB3T3245DGVR
SSOP (QSOP) – DBQ
TSSOP – PW
CB3T3245
KS245
–40°C to 85°C
Tape and reel
Tape and reel
TVSOP – DGV
KS245
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
Z
A port = B port
Disconnect
H
2
SN74CB3T3245
8-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS136–OCTOBER 2003–REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
2
18
A1
B1
SW
9
11
A8
B8
SW
19
OE
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
A
B
(1)
V
G
Control
Circuit
(2)
EN
1) Gate Voltage (V ) is approximately equal to V + V when the switch is ON and V > (V + V ).
G
CC
T
I
CC
T
2) EN is the internal enable signal applied to the switch.
3
SN74CB3T3245
8-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS136–OCTOBER 2003–REVISED MARCH 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
VCC
VIN
VI/O
IIK
Supply voltage range(2)
7
V
Control input voltage range(2)(3)
Switch I/O voltage range(2)(3)(4)
Control input clamp current
I/O port clamp current
7
7
V
V
VIN < 0
VI/O < 0
–50
–50
±128
±100
68
mA
mA
mA
mA
II/OK
II/O
ON-state switch current(5)
Continuous current through VCC or GND
DBQ package
DGV package
DW package
PW package
92
θJA
Package thermal impedance(6)
°C/W
°C
58
83
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VI and VO are used to denote specific conditions for VI/O
(5) II and IO are used to denote specific conditions for II/O
.
.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
2.3
1.7
2
MAX
3.6
5.5
5.5
0.7
0.8
5.5
85
UNIT
VCC
VIH
Supply voltage
V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
High-level control input voltage
V
V
0
VIL
Low-level control input voltage
0
VI/O
TA
Data input/output voltage
0
V
Operating free-air temperature
–40
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74CB3T3245
8-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS136–OCTOBER 2003–REVISED MARCH 2005
Electrical Characteristics(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(2)
MAX UNIT
VIK
VOH
IIN
VCC = 3 V, II = –18 mA
–1.2
V
See Figure 3 and Figure 4
Control inputs VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND
±10
±20
–40
±5
µA
µA
VI = VCC – 0.7 V to 5.5 V
II
VCC = 3.6 V, Switch ON, VIN = VCC or GND VI = 0.7 V to VCC – 0.7 V
VI = 0 to 0.7 V
(3)
IOZ
Ioff
VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND
VCC = 0, VO = 0 to 5.5 V, VI = 0,
±10
10
µA
µA
VI = VCC or GND
VI = 5.5 V
40
VCC = 3.6 V, II/O = 0,
Switch ON or OFF, VIN = VCC or GND
ICC
µA
40
(4)
∆ICC
Control inputs VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND
Control inputs VCC = 3.3 V, VIN = VCC or GND
300
µA
pF
pF
Cin
4
5
Cio(OFF)
VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF, VIN = VCC or GND
VI/O = 5.5 V or 3.3 V
VCC = 3.3 V, Switch ON, VIN = VCC or GND
VI/O = GND
5
Cio(ON)
pF
13
5
IO = 24 mA
VCC = 2.3 V, TYP at VCC = 2.5 V, VI = 0
IO = 16 mA
8.5
8.5
7
5
(5)
ron
Ω
IO = 64 mA
5
VCC = 3 V, VI = 0
IO = 32 mA
5
7
(1) VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
(2) All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
(5) Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
(1)
tpd
A or B
OE
B or A
A or B
A or B
0.15
10.5
5.5
0.25
8
ns
ns
ns
ten
1
1
1
1
tdis
OE
7.5
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
5
SN74CB3T3245
8-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS136–OCTOBER 2003–REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
CC
Input Generator
S1
Open
R
L
V
I
V
O
GND
50 Ω
50 Ω
V
G2
C
L
R
L
(see Note A)
S1
V
I
C
L
V
∆
R
L
V
CC
TEST
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V or GND
5.5 V or GND
30 pF
50 pF
t
pd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × V
2 × V
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
CC
t
/t
PLZ PZL
CC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V
5.5 V
30 pF
50 pF
0.15 V
0.3 V
t
/t
PHZ PZH
Output
Control
V
CC
V /2
CC
V /2
CC
(V )
IN
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
Output
Control
V
CC
V /2
CC
S1 at 2 × V
V + V
∆
OL
V /2
CC
V /2
CC
CC
(V )
IN
(see Note B)
OL
0 V
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
V
OH
− V
∆
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
en
are the same as t
. The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
pd(s)
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Test Circuit and Voltage Waveforms
6
SN74CB3T3245
8-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS136–OCTOBER 2003–REVISED MARCH 2005
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
4.0
4.0
3.0
2.0
1.0
0.0
V
= 2.3 V
= 1 µA
= 25°C
V
= 3 V
CC
CC
I
O
I
O
= 1 µA
T = 25°C
A
T
A
3.0
2.0
1.0
0.0
0.0
2.0
4.0
6.0
1.0
3.0
5.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 3. Data Output Voltage vs Data Input Voltage
7
SN74CB3T3245
8-BIT FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
www.ti.com
SCDS136–OCTOBER 2003–REVISED MARCH 2005
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE HIGH
vs
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
4.0
3.5
4.0
3.5
3.0
V
= 2.3 V to 3.6 V
V
= 2.3 V to 3.6 V
CC
CC
V = 5.5 V
I
T = 85°C
A
V = 5.5 V
I
T = 25°C
A
100 µA
100 µA
8 mA
16 mA
24 mA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.5
2.0
1.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4.0
3.5
3.0
2.5
2.0
V
= 2.3 V to 3.6 V
CC
V = 5.5 V
100 µA
I
T = –40°C
A
8 mA
16 mA
24 mA
1.5
3.3
− Supply Voltage − V
2.3
2.5
2.7
2.9
3.1
3.5
3.7
V
CC
Figure 4. VOH Values
8
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
74CB3T3245DBQRE4
74CB3T3245DGVRE4
SN74CB3T3245DBQR
SN74CB3T3245DGVR
SN74CB3T3245DW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
20
20
20
20
20
20
20
20
20
20
20
20
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
TVSOP
DGV
DBQ
DGV
DW
DW
DW
DW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
TVSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CB3T3245DWE4
SN74CB3T3245DWR
SN74CB3T3245DWRE4
SN74CB3T3245PW
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CB3T3245PWE4
SN74CB3T3245PWR
SN74CB3T3245PWRE4
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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