SN74CB3T3383PWRG4_技术文档

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SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004

D

Output Voltage Translation Tracks V

D

V

Operating Range From 2.3 V to 3.6 V

CC

Supports Mixed-Mode Signal Operation On

All Data I/O Ports

− 5-V Input Down To 3.3-V Output Level

Data I/Os Support 0- to 5-V Signaling

Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V,

5 V)

Shift With 3.3-V V

− 5-V/3.3-V Input Down To 2.5-V Output

Level Shift With 2.5-V V

CC

D

Control Inputs Can Be Driven by TTL or

5-V/3.3-V CMOS Outputs

CC

I

Supports Partial-Power-Down Mode

off

D

5-V-Tolerant I/Os With Device Powered Up

or Powered Down

Operation

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Bidirectional Data Flow, With Near-Zero

Propagation Delay

ESD Performance Tested Per JESD 22

− 2000-V Human-Body Model

(A114-B, Class II)

Low ON-State Resistance (r

)

on

Characteristics (r = 5 Ω Typical)

on

Low Input/Output Capacitance Minimizes

− 1000-V Charged-Device Model (C101)

Loading (C

= 8 pF Typical)

io(OFF)

D

Supports Digital Applications: Level

Translation, Memory Interleaving, Bus

Isolation

Data and Control Inputs Provide

Undershoot Clamp Diodes

Low Power Consumption

Ideal for Low-Power Portable Equipment

(I

= 20 µA Max)

CC

DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

1

24

23

22

21

20

19

18

17

16

15

14

13

BE

1B1

1A1

1A2

1B2

2B1

2A1

2A2

2B2

3B1

3A1

GND

V

CC

2

5B2

5A2

5A1

5B1

4B2

4A2

4A1

4B1

3B2

3A2

BX

3

4

5

6

7

8

9

10

11

12

description/ordering information

ORDERING INFORMATION

ORDERABLE

TOP-SIDE

MARKING

†

PACKAGE

T

A

PART NUMBER

SN74CB3T3383DW

SN74CB3T3383DWR

SN74CB3T3383DBQR

SN74CB3T3383PW

SN74CB3T3383PWR

SN74CB3T3383DGVR

Tube

SOIC − DW

CB3T3383

Tape and reel

Tube

SSOP (QSOP) − DBQ

−40°C to 85°C

TSSOP − PW

TVSOP − DGV

KS383

Tape and reel

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2004, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢕꢖ ꢗꢋꢘ ꢙꢆ ꢖ ꢆ ꢋꢘ ꢚ ꢛꢔꢋꢘ ꢛꢚꢇꢒꢓ ꢎ ꢅꢏ ꢀ ꢀ ꢔꢌ ꢇ ꢄꢑ ꢔ ꢌꢇ ꢑ ꢗ ꢋꢘꢋꢇꢛ ꢚ ꢎꢜꢒꢁꢇ ꢚ ꢎꢘꢎ ꢚ ꢀꢑꢌ ꢍ ꢇꢎ ꢜ

SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004

description/ordering information (continued)

The SN74CB3T3383 is a high-speed TTL-compatible FET bus-exchange switch with low ON-state resistance

(r ), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data

on

I/O ports by providing voltage translation that tracks V . The SN74CB3T3383 supports systems using 5-V

CC

TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels

(see Figure 1).

V

CC

5.5 V

V

≈V

CC

IN

OUT

CC

≈V

CC

− 1 V

CC

CB3T

0 V

Input Voltages

Output Voltages

NOTE A: If the input high voltage (V ) level is greater than or equal to V

IH CC

− 1 V, and less than or equal to 5.5 V, then the output high

) level will be equal to approximately the V voltage level.

voltage (V

OH

CC

Figure 1. Typical DC Voltage Translation Characteristics

The SN74CB3T3383 is organized as a 10-bit bus switch or as a 5-bit bus-exchange with enable (BE) input.

When used as a 5-bit bus-exchange, the device provides data exchanging between four signal ports. When BE

is low, the bus-exchange switch is ON, and the select input (BX) controls the data path. When BE is high, the

bus-exchange switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using I . The I feature ensures that

off

damaging current will not backflow through the device when it is powered down. The device has isolation during

power off.

To ensure the high-impedance state during power up or power down, BE should be tied to V

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup

CC

2

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SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004

FUNCTION TABLE

(each 5-bit switch)

INPUTS

BE BX

INPUTS/OUTPUTS

FUNCTION

A1

A2

A1 port = B1 port

A2 port = B2 port

L

B1

B2

A1 port = B2 port

A2 port = B1 port

L

H

X

B2

Z

B1

Z

H

Disconnect

logic diagram (positive logic)

3

2

1A1

1B1

SW

4

5

1A2

1B2

5B1

SW

21

20

5A1

SW

22

23

5A2

5B2

SW

1

BE

13

BX

3

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SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004

simplified schematic, each FET switch (SW)

A

B

†

V

G

Control

Circuit

‡

EN

†

‡

Gate Voltage (V ) is approximately equal to V

CC

EN is the internal enable signal applied to the switch.

+ V when the switch is ON and V > V

+ V .

T

G

T

I

CC

§

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

IN

I/O

IK IN

I/O port clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

I/OK I/O

ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Continuous current through V

I/O

or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

CC

Package thermal impedance, θ (see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W

JA

DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W

DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

§

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltages are with respect to ground unless otherwise specified.

2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. V and V are used to denote specific conditions for V

I/O

.

I

O

4. I and I are used to denote specific conditions for I .

I

O

I/O

5. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 6)

MIN

2.3

1.7

2

MAX

3.6

5.5

0.7

0.8

5.5

85

UNIT

V

Supply voltage

V

CC

V

CC

V

CC

V

CC

V

CC

= 2.3 V to 2.7 V

= 2.7 V to 3.6 V

= 2.3 V to 2.7 V

= 2.7 V to 3.6 V

High-level control input voltage

V

IH

0

V

Low-level control input voltage

IL

0

Data input/output voltage

0

V

I/O

T

A

Operating free-air temperature

−40

°C

NOTE 6: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

4

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SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

V

= 3 V,

CC

V

−1.2

V

IK

I = −18 mA

I

See Figures 3 and 4

OH

‡

V

= 3.6 V,

= 3.6 V to 5.5 V or GND

CC

IN

I

IN

Control inputs

10

µA

‡

V = V

CC

− 0.7 V to 5.5 V

− 0.7 V

20

−40

5

I

V

CC

= 3.6 V,

V = 0.7 V to V

I CC

Switch ON,

I

V

IN

= V

or GND

CC

V = 0 to 0.7 V

I

V

= 3.6 V,

= 0 to 5.5 V,

CC

O

§

V = 0,

I

10

µA

I

OZ

Switch OFF,

V

= V or GND

CC

IN

V

= 0,

CC

= 0 to 5.5 V,

I

µA

off

O

V = 0,

I

V

= 3.6 V,

CC

= 0,

V = V

CC

or GND

20

I

I/O

Switch ON or OFF,

CC

V = 5.5 V

I

V

IN

= V

or GND

CC

V

= 3 V to 3.6 V,

CC

¶

∆I

CC

Control inputs One input at V

− 0.6 V,

300

µA

CC

Other inputs at V

or GND

CC

V

= 3.3 V,

CC

IN

C

Control inputs

4

pF

in

= V

or GND

CC

V

CC

V

I/O

= 3.3 V,

= 5.5 V, 3.3 V, or GND,

8

7

pF

io(OFF)

io(ON)

Switch OFF,

V

IN

= V

or GND

CC

V

CC

= 3.3 V,

V

I

= 5.5 V or 3.3 V

= GND

I/O

Switch ON,

C

21

5

V

IN

= V

or GND

I/O

CC

V

= 2.3 V,

= 24 mA

9

CC

O

TYP at V

= 2.5 V,

CC

I

O

= 16 mA

5

V = 0

I

#

Ω

r

on

I

= 64 mA

= 32 mA

5

8

V

= 3 V,

O

CC

V = 0

I

O

†

‡

§

¶

#

All typical values are at V

CC

= 3.3 V (unless otherwise noted), T = 25°C.

A

V

and I refer to control inputs. V , V , I , and I refer to data pins.

IN

I

O

I

O

For I/O ports, the parameter I

includes the input leakage current.

This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V

OZ

or GND.

CC

Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the

lower of the voltages of the two (A or B) terminals.

5

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SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 2)

V

= 2.5 V

V

= 3.3 V

CC

0.2 V

CC

0.3 V

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

MIN MAX

†

A or B

BX

B or A

A or B

0.15

15

0.25

10

t

pd

ns

1

pd(s)

en

13.5

7

9

ns

BE

8.5

BE

dis

†

The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,

when driven by an ideal voltage source (zero output impedance).

6

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SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004

PARAMETER MEASUREMENT INFORMATION

V

CC

Input Generator

V

IN

50 Ω

V

G1

TEST CIRCUIT

DUT

2 × V

CC

Open

Input Generator

50 Ω

S1

R

V

O

L

I

GND

50 Ω

V

G2

C

R

L

(see Note A)

S1

V

I

V

∆

C

R

V

CC

TEST

L

2.5 V 0.2 V

3.3 V 0.3 V

Open

500 Ω

3.6 V or GND

5.5 V or GND

30 pF

50 pF

t

pd(s)

2.5 V 0.2 V

3.3 V 0.3 V

2 × V

500 Ω

GND

30 pF

50 pF

0.15 V

0.3 V

CC

t

/t

PLZ PZL

2.5 V 0.2 V

3.3 V 0.3 V

Open

500 Ω

3.6 V

5.5 V

30 pF

50 pF

0.15 V

0.3 V

t

/t

PHZ PZH

Output

Control

V

CC

V

CC

/2

V

CC

/2

(V

IN

)

0 V

t

PLZ

PZL

Output

Waveform 1

V

CC

Output

Control

V

CC

V

/2

CC

S1 at 2 × V

(see Note B)

V

+ V

V

CC

/2

V

CC

/2

CC

OL

∆

(V

IN

)

OL

0 V

t

PZH

PHZ

t

PLH

PHL

Output

Waveform 2

S1 at Open

(see Note B)

V

OH

V

OH

− V

OH

∆

V

/2

Output

CC

V

CC

/2

V

CC

/2

0 V

V

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (t

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

)

pd(s)

C includes probe and jig capacitance.

L

NOTES: A.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

O

r

f

D. The outputs are measured one at a time, with one transition per measurement.

E.

F.

G.

t

and t

are the same as t

.

dis

PLZ

PZL

PLH

PHZ

PZH

PHL

are the same as t

.

en

. The t propagation delay is the calculated RC time constant of the typical ON-state resistance

pd

pd(s)

of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

H. All parameters and waveforms are not applicable to all devices.

Figure 2. Test Circuit and Voltage Waveforms

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆ ꢆꢈ ꢆ

ꢉꢊ ꢋꢅꢌ ꢇ ꢍ ꢎꢇ ꢅ ꢏꢀ ꢋꢎ ꢐꢄ ꢑꢒꢁ ꢓꢎ ꢀ ꢔꢌ ꢇ ꢄꢑ

ꢕꢖ ꢗꢋꢘ ꢙꢆ ꢖ ꢆ ꢋꢘ ꢚ ꢛꢔꢋꢘ ꢛꢚꢇꢒꢓ ꢎ ꢅꢏ ꢀ ꢀ ꢔꢌ ꢇ ꢄꢑ ꢔ ꢌꢇ ꢑ ꢗ ꢋꢘꢋꢇꢛ ꢚ ꢎꢜꢒꢁꢇ ꢚ ꢎꢘꢎ ꢚ ꢀꢑꢌ ꢍ ꢇꢎ ꢜ

SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS

OUTPUT VOLTAGE

vs

INPUT VOLTAGE

4.0

3.0

2.0

1.0

0.0

4.0

3.0

2.0

1.0

V

= 2.3 V

V

= 3 V

CC

= 1 µA

CC

I

T

I

O

= 1 µA

T = 25°C

A

O

= 25°C

A

0.0

2.0

4.0

6.0

1.0

3.0

5.0

0.0

1.0

2.0

3.0

4.0

5.0

6.0

V − Input Voltage − V

I

V − Input Voltage − V

I

Figure 3. Data Output Voltage vs Data Input Voltage

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢆꢆ ꢈꢆ

ꢉ ꢊ ꢋꢅꢌ ꢇ ꢍ ꢎꢇ ꢅꢏꢀ ꢋꢎꢐꢄ ꢑꢒꢁꢓ ꢎ ꢀ ꢔꢌ ꢇꢄ ꢑ

ꢕ ꢖ ꢗ ꢋꢘꢙ ꢆ ꢖ ꢆ ꢋꢘ ꢚꢛ ꢔꢋꢘ ꢛꢚꢇꢒꢓ ꢎ ꢅꢏꢀ ꢀꢔ ꢌ ꢇꢄ ꢑ ꢔ ꢌꢇ ꢑ ꢗ ꢋꢘꢋꢇꢛ ꢚ ꢎꢜꢒꢁꢇ ꢚ ꢎꢘꢎ ꢚ ꢀ ꢑꢌ ꢍꢇ ꢎꢜ

SCDS158A − OCTOBER 2003 − REVISED DECEMBER 2004

TYPICAL CHARACTERISTICS (continued)

OUTPUT VOLTAGE HIGH

vs

OUTPUT VOLTAGE HIGH

vs

SUPPLY VOLTAGE

4.0

3.5

4.0

V

= 2.3 V to 3.6 V

V

= 2.3 V to 3.6 V

CC

V = 5.5 V

CC

V = 5.5 V

I

100 µA

T

= 85°C

3.5

3.0

2.5

2.0

1.5

T

= 25°C

A

8 mA

16 mA

24 mA

8 mA

16 mA

24 mA

3.0

2.5

2.0

1.5

2.3

2.5

2.7

CC

2.9

3.1

3.3

3.5

3.7

2.3

2.5

2.7

2.9

3.1

3.3

3.5

3.7

V

− Supply Voltage − V

V

CC

− Supply Voltage − V

OUTPUT VOLTAGE HIGH

vs

SUPPLY VOLTAGE

4.0

3.5

3.0

2.5

2.0

1.5

V

= 2.3 V to 3.6 V

CC

V = 5.5 V

I

100 µA

T

= –40°C

A

8 mA

16 mA

24 mA

3.3

− Supply Voltage − V

2.3

2.5

2.7

2.9

3.1

3.5

3.7

V

CC

Figure 4. V

Values

OH

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

24-May-2007

PACKAGING INFORMATION

Orderable Device

74CB3T3383DBQRE4

74CB3T3383DBQRG4

74CB3T3383DGVRE4

74CB3T3383DGVRG4

SN74CB3T3383DBQR

SN74CB3T3383DGVR

SN74CB3T3383DW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SSOP/

QSOP

DBQ

24

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SSOP/

QSOP

DBQ

DGV

DBQ

DGV

DW

PW

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TVSOP

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TVSOP

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SSOP/

QSOP

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TVSOP

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74CB3T3383DWE4

SN74CB3T3383DWG4

SN74CB3T3383DWR

SN74CB3T3383DWRE4

SN74CB3T3383DWRG4

SN74CB3T3383PW

SOIC

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74CB3T3383PWE4

SN74CB3T3383PWG4

SN74CB3T3383PWR

SN74CB3T3383PWRE4

SN74CB3T3383PWRG4

PW

60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PW

60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-May-2007

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jul-2007

TAPE AND REEL INFORMATION

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jul-2007

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

(mm)

16

SN74CB3T3383DBQR

SN74CB3T3383DGVR

SN74CB3T3383DWR

SN74CB3T3383PWR

DBQ

DGV

DW

24

MLA

TAI

6.5

7.0

9.0

5.6

2.1

1.6

2.7

1.6

8

16

12

24

16

Q1

12

24

10.75

6.95

15.7

8.3

12

8

PW

MLA

16

TAPE AND REEL BOX INFORMATION

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

SN74CB3T3383DBQR

SN74CB3T3383DGVR

SN74CB3T3383DWR

SN74CB3T3383PWR

DBQ

DGV

DW

24

MLA

TAI

346.0

33.0

29.0

41.0

33.0

PW

MLA

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jul-2007

Pack Materials-Page 3

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

M

0,07

0,40

24

13

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

1

12

0,50

A

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

14

16

20

24

38

48

56

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,

improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.

Customers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s

standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this

warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily

performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Data Converters

DSP

Applications

Audio

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/audio

Automotive

Broadband

Digital Control

Military

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

interface.ti.com

logic.ti.com

Logic

Power Mgmt

Microcontrollers

RFID

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/lpw

Telephony

Low Power

Wireless

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SN74CB3T3383PWRG4
厂家：	TEXAS INSTRUMENTS
描述：	10-BIT FET BUS-EXCHANGE SWITCH 2.5V/3.3-V LOW-VOLTAGE BUSSWITCH WITH 5-V-TOLERANT LEVEL SHIFTER 10位FET总线交换开关2.5V / 3.3 -V与5 V容限电平转换器低电压BUSSWITCH 总线驱动器总线收发器转换器电平转换器开关逻辑集成电路光电二极管
文件：	总19页 (文件大小：401K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74CB3T3383PWRG4 [TI]

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