SN74CB3T3384PWRG4 [TI]
具有 2 个控制输入和电平转换器的 3.3V、1:1 (SPST)、10 通道通用 FET 总线开关 | PW | 24 | -40 to 85;
| 型号： | SN74CB3T3384PWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 2 个控制输入和电平转换器的 3.3V、1:1 (SPST)、10 通道通用 FET 总线开关 | PW | 24 | -40 to 85 开关 驱动 光电二极管 逻辑集成电路 总线驱动器 总线收发器 转换器 电平转换器 |
| 文件： | 总15页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢉ ꢊ ꢋꢅꢌ ꢇ ꢍ ꢎꢇ ꢅꢏ ꢀ ꢀ ꢐꢌ ꢇꢄ ꢑ
ꢌꢇ ꢑ ꢔ ꢋꢕꢋꢇꢘ ꢗ ꢎꢛꢙꢁꢇ ꢗ ꢎꢕꢎ ꢗ ꢀ ꢑꢌ ꢍꢇ ꢎꢛ
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SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
D
D
Output Voltage Translation Tracks V
D
D
V
Operating Range From 2.3 V to 3.6 V
CC
CC
Supports Mixed-Mode Signal Operation On
All Data I/O Ports
− 5-V Input Down To 3.3-V Output Level
Data I/Os Support 0 to 5-V Signaling Levels
(For Example: 0.8-V, 1.2-V, 1.5-V, 1.8-V,
2.5-V, 3.3-V, 5-V)
Shift With 3.3-V V
− 5-V/3.3-V Input Down To 2.5-V Output
Level Shift With 2.5-V V
CC
D
D
D
D
Control Inputs Can Be Driven by TTL or
5-V/3.3-V/2.5-V CMOS Outputs
CC
I
Supports Partial-Power-Down Mode
off
D
D
D
D
D
D
5-V-Tolerant I/Os With Device Powered-Up
or Powered-Down
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bidirectional Data Flow, With Near-Zero
Propagation Delay
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
Low ON-State Resistance (r
)
on
Characteristics (r = 5 Ω Typical)
on
Low Input/Output Capacitance Minimizes
− 1000-V Charged-Device Model (C101)
Loading (C
= 5 pF Typical)
io(OFF)
D
D
Supports Digital Applications: Level
Translation, Memory Interleaving, Bus
Isolation
Data and Control Inputs Provide
Undershoot Clamp Diodes
Low Power Consumption
Ideal for Low-Power Portable Equipment
(I
= 40 µA Max)
CC
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1
24
23
22
21
20
19
18
17
16
15
14
13
1OE
1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
1B5
1A5
GND
V
CC
2
2B5
2A5
2A4
2B4
2B3
2A3
2A2
2B2
2B1
2A1
2OE
3
4
5
6
7
8
9
10
11
12
description/ordering information
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SN74CB3T3384DW
SN74CB3T3384DWR
SN74CB3T3384DBQR
SN74CB3T3384PW
SN74CB3T3384PWR
SN74CB3T3384DGVR
Tube
SOIC − DW
CB3T3384
CB3T3384
Tape and reel
Tape and reel
Tube
SSOP (QSOP) − DBQ
−40°C to 85°C
TSSOP − PW
TVSOP − DGV
KS384
Tape and reel
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆ ꢆꢈ ꢃ
ꢉꢊ ꢋꢅꢌ ꢇ ꢍ ꢎꢇ ꢅ ꢏ ꢀ ꢀ ꢐꢌ ꢇ ꢄꢑ
ꢒꢓ ꢔꢋꢕ ꢖꢆ ꢓ ꢆ ꢋꢕ ꢗ ꢘꢐꢋꢕ ꢘꢗꢇꢙꢚ ꢎ ꢅꢏ ꢀ ꢀ ꢐꢌ ꢇ ꢄꢑ ꢐ ꢌꢇ ꢑ ꢔ ꢋꢕꢋꢇꢘ ꢗꢎ ꢛꢙꢁꢇ ꢗ ꢎꢕꢎ ꢗ ꢀꢑꢌ ꢍ ꢇꢎ ꢛ
SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
description/ordering information (continued)
The SN74CB3T3384 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r ),
on
allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O
ports by providing voltage translation that tracks V . The SN74CB3T3384 supports systems using 5-V TTL,
CC
3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
V
CC
5.5 V
V
≈V
≈V
CC
IN
OUT
CC
≈V
CC
− 1 V
− 1 V
CC
CB3T
0 V
0 V
Input Voltages
Output Voltages
NOTE A: If the input high voltage (V ) level is greater than or equal to V
IH CC
− 1 V, and less than or equal to 5.5 V, the output high
) level will be equal to approximately the V voltage level.
voltage (V
OH
CC
Figure 1. Typical DC-Voltage-Translation Characteristics
The SN74CB3T3384 is organized as two 5-bit bus switches with separate ouput-enable (1OE, 2OE) inputs. It
can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE is low, the associated 5-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
FUNCTION TABLE
(each 5-bit bus switch)
INPUT INPUT/OUTPUT
FUNCTION
OE
L
A
B
Z
A port = B port
Disconnect
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
logic diagram (positive logic)
3
2
1A1
1B1
SW
SW
11
1
10
1A5
1OE
1B5
14
15
23
2A1
2B1
2B5
SW
SW
22
13
2A5
2OE
simplified schematic, each FET switch (SW)
†
Gate Voltage (V
)
is approximately
G
equal to V
and V > V
CC
+ V when the switch is ON
+ V .
T
CC
T
I
A
B
†
V
G
Control
Circuit
‡
EN
‡
EN is the internal enable signal applied to the switch.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆ ꢆꢈ ꢃ
ꢉꢊ ꢋꢅꢌ ꢇ ꢍ ꢎꢇ ꢅ ꢏ ꢀ ꢀ ꢐꢌ ꢇ ꢄꢑ
ꢒꢓ ꢔꢋꢕ ꢖꢆ ꢓ ꢆ ꢋꢕ ꢗ ꢘꢐꢋꢕ ꢘꢗꢇꢙꢚ ꢎ ꢅꢏ ꢀ ꢀ ꢐꢌ ꢇ ꢄꢑ ꢐ ꢌꢇ ꢑ ꢔ ꢋꢕꢋꢇꢘ ꢗꢎ ꢛꢙꢁꢇ ꢗ ꢎꢕꢎ ꢗ ꢀꢑꢌ ꢍ ꢇꢎ ꢛ
SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IN
I/O
IK IN
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/OK I/O
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Continuous current through V
I/O
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
I/O
.
I
O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN
2.3
1.7
2
MAX
3.6
5.5
5.5
0.7
0.8
5.5
85
UNIT
V
V
Supply voltage
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
High-level control input voltage
V
V
IH
0
V
V
Low-level control input voltage
IL
0
Data input/output voltage
0
V
I/O
T
A
Operating free-air temperature
−40
°C
NOTE 6: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢉ ꢊ ꢋꢅꢌ ꢇ ꢍ ꢎꢇ ꢅꢏ ꢀ ꢀ ꢐꢌ ꢇꢄ ꢑ
ꢒ ꢓ ꢔ ꢋꢕꢖ ꢆ ꢓ ꢆ ꢋꢕ ꢗꢘ ꢐꢋꢕ ꢘꢗꢇꢙꢚ ꢎ ꢅꢏꢀ ꢀꢐ ꢌ ꢇꢄ ꢑ ꢐ ꢌꢇ ꢑ ꢔ ꢋꢕꢋꢇꢘ ꢗ ꢎꢛꢙꢁꢇ ꢗ ꢎꢕꢎ ꢗ ꢀ ꢑꢌ ꢍꢇ ꢎꢛ
SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
= 3 V,
CC
V
V
−1.2
V
IK
I = −18 mA
I
See Figures 3 and 4
OH
V
V
= 3.6 V,
= 3.6 V to 5.5 V or GND
CC
IN
I
Control inputs
10
µA
µA
IN
V = V
CC
− 0.7 V to 5.5 V
− 0.7 V
20
−40
5
I
V
CC
= 3.6 V,
V = 0.7 V to V
I CC
Switch ON,
I
I
V
IN
= GND
V = 0 to 0.7 V
I
V
V
= 3.6 V,
= 0 to 5.5 V,
CC
O
‡
V = 0,
I
10
10
µA
I
OZ
Switch OFF,
V
= V
CC
IN
V
V
V = 0
I
= 0,
CC
= 0 to 5.5 V,
I
I
µA
µA
off
O
V
= 3.6 V,
CC
= 0,
V = V
CC
or GND
40
40
I
I
I/O
Switch ON or OFF,
CC
V = 5.5 V
I
V
IN
= V
or GND
CC
V
= 3 V to 3.6 V,
CC
§
∆I
CC
Control inputs One input at V
− 0.6 V,
300
µA
CC
Other inputs at V
or GND
CC
V
V
= 3.3 V,
CC
IN
C
C
Control inputs
3
pF
in
= V
or GND
CC
V
CC
V
I/O
= 3.3 V,
= 5.5 V, 3.3 V, or GND,
5
4
pF
pF
io(OFF)
io(ON)
Switch OFF,
V
IN
= V
CC
V
CC
= 3.3 V,
V
V
I
= 5.5 V or 3.3 V
= GND
I/O
Switch ON,
C
12
5
V
IN
= GND
I/O
V
= 2.3 V,
= 24 mA
8
8
CC
O
TYP at V
= 2.5 V,
CC
I
O
= 16 mA
5
V = 0
I
¶
Ω
r
on
I
I
= 64 mA
= 32 mA
5
5
7
7
V
= 3 V,
O
CC
V = 0
I
O
V
†
‡
§
¶
and I refer to control inputs. V , V , I , and I refer to data pins.
IN
IN
I
O
I
O
All typical values are at V
= 3.3 V (unless otherwise noted), T = 25°C.
CC
For I/O ports, the parameter I
A
includes the input leakage current.
OZ
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the
lower of the voltages of the two (A or B) terminals.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆ ꢆꢈ ꢃ
ꢉꢊ ꢋꢅꢌ ꢇ ꢍ ꢎꢇ ꢅ ꢏ ꢀ ꢀ ꢐꢌ ꢇ ꢄꢑ
ꢒꢓ ꢔꢋꢕ ꢖꢆ ꢓ ꢆ ꢋꢕ ꢗ ꢘꢐꢋꢕ ꢘꢗꢇꢙꢚ ꢎ ꢅꢏ ꢀ ꢀ ꢐꢌ ꢇ ꢄꢑ ꢐ ꢌꢇ ꢑ ꢔ ꢋꢕꢋꢇꢘ ꢗꢎ ꢛꢙꢁꢇ ꢗ ꢎꢕꢎ ꢗ ꢀꢑꢌ ꢍ ꢇꢎ ꢛ
SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 2)
V
= 2.5 V
V
= 3.3 V
CC
0.2 V
CC
0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
†
t
t
t
A or B
OE
B or A
A or B
A or B
0.15
10.5
6.5
0.25
7.5
8
ns
ns
ns
pd
en
1
1
1
1
OE
dis
†
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢆꢆ ꢈꢃ
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ꢒ ꢓ ꢔ ꢋꢕꢖ ꢆ ꢓ ꢆ ꢋꢕ ꢗꢘ ꢐꢋꢕ ꢘꢗꢇꢙꢚ ꢎ ꢅꢏꢀ ꢀꢐ ꢌ ꢇꢄ ꢑ ꢐ ꢌꢇ ꢑ ꢔ ꢋꢕꢋꢇꢘ ꢗ ꢎꢛꢙꢁꢇ ꢗ ꢎꢕꢎ ꢗ ꢀ ꢑꢌ ꢍꢇ ꢎꢛ
SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
CC
Open
Input Generator
50 Ω
S1
R
V
V
O
L
I
GND
50 Ω
V
G2
C
R
L
L
(see Note A)
S1
V
I
V
∆
C
R
V
CC
TEST
L
L
2.5 V 0.2 V
3.3 V 0.3 V
2 × V
2 × V
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
CC
CC
t
/t
PLZ PZL
2.5 V 0.2 V
3.3 V 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V
5.5 V
30 pF
50 pF
0.15 V
0.3 V
t
/t
PHZ PZH
Output
Control
V
CC
V
CC
/2
V
CC
/2
(V
IN
)
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
V
CC
/2
S1 at 2 × V
(see Note B)
V
+ V
OL
CC
∆
OL
t
t
PZH
PHZ
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
− V
∆
V
CC
/2
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
t
t
and t
and t
are the same as t
.
dis
PLZ
PZL
PHZ
PZH
are the same as t
.
en
Figure 2. Test Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢆ ꢆꢈ ꢃ
ꢉꢊ ꢋꢅꢌ ꢇ ꢍ ꢎꢇ ꢅ ꢏ ꢀ ꢀ ꢐꢌ ꢇ ꢄꢑ
ꢒꢓ ꢔꢋꢕ ꢖꢆ ꢓ ꢆ ꢋꢕ ꢗ ꢘꢐꢋꢕ ꢘꢗꢇꢙꢚ ꢎ ꢅꢏ ꢀ ꢀ ꢐꢌ ꢇ ꢄꢑ ꢐ ꢌꢇ ꢑ ꢔ ꢋꢕꢋꢇꢘ ꢗꢎ ꢛꢙꢁꢇ ꢗ ꢎꢕꢎ ꢗ ꢀꢑꢌ ꢍ ꢇꢎ ꢛ
SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
INPUT VOLTAGE
4.0
3.0
2.0
4.0
3.0
2.0
1.0
0.0
V
= 2.3 V
V
= 3 V
CC
= 1 µA
CC
I
T
I
O
= 1 µA
T = 25°C
A
O
= 25°C
A
1.0
0.0
0.0
2.0
4.0
6.0
1.0
3.0
5.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 3. Data Output Voltage vs Data Input Voltage
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢆꢆ ꢈꢃ
ꢉ ꢊ ꢋꢅꢌ ꢇ ꢍ ꢎꢇ ꢅꢏ ꢀ ꢀ ꢐꢌ ꢇꢄ ꢑ
ꢒ ꢓ ꢔ ꢋꢕꢖ ꢆ ꢓ ꢆ ꢋꢕ ꢗꢘ ꢐꢋꢕ ꢘꢗꢇꢙꢚ ꢎ ꢅꢏꢀ ꢀꢐ ꢌ ꢇꢄ ꢑ ꢐ ꢌꢇ ꢑ ꢔ ꢋꢕꢋꢇꢘ ꢗ ꢎꢛꢙꢁꢇ ꢗ ꢎꢕꢎ ꢗ ꢀ ꢑꢌ ꢍꢇ ꢎꢛ
SCDS159B − OCTOBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE HIGH
vs
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
4.0
3.5
3.0
V
= 2.3 V ~ 3.6 V
V
= 2.3 V ~ 3.6 V
CC
V = 5.5 V
CC
V = 5.5 V
I
I
100 µA
100 µA
T
= 85°C
T
= 25°C
A
A
8 mA
16 mA
24 mA
8 mA
16 mA
24 mA
2.5
2.0
1.5
2.3
2.5
2.7
CC
2.9
3.1
3.3
3.5
3.7
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
V
− Supply Voltage − V
V
CC
− Supply Voltage − V
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
V
= 2.3 V to 3.6 V
CC
V = 5.5 V
I
100 µA
T
= -40°C
A
8 mA
16 mA
24 mA
3.3
− Supply Voltage − V
2.3
2.5
2.7
2.9
3.1
3.5
3.7
V
CC
Figure 4. V
Values
OH
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jun-2005
PACKAGING INFORMATION
Orderable Device
74CB3T3384DBQRE4
SN74CB3T3384DBQR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
24
2500
2500
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SSOP/
QSOP
DBQ
24
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74CB3T3384DGVR
SN74CB3T3384DW
PREVIEW
ACTIVE
TVSOP
SOIC
DGV
DW
24
24
TBD
Call TI
Call TI
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CB3T3384DWE4
SN74CB3T3384DWR
SN74CB3T3384DWRE4
SN74CB3T3384PW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
DW
PW
PW
PW
PW
24
24
24
24
24
24
24
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
60
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
SN74CB3T3384PWE4
SN74CB3T3384PWR
SN74CB3T3384PWRE4
60
Pb-Free
(RoHS)
2000
2000
Pb-Free
(RoHS)
Pb-Free
(RoHS)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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