SN74CBT16211DL [TI]
24-Bit Bus-Exchange Switch 56-SSOP -40 to 85;
| 型号： | SN74CBT16211DL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-Bit Bus-Exchange Switch 56-SSOP -40 to 85 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总5页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBT16211
24-BIT BUS SWITCH
SCDS028E – JULY 1995 – REVISED APRIL 1997
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input and Output Levels
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
NC
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
1A11
1A12
2A1
2A2
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
1B11
1B12
2B1
2B2
2B3
GND
2B4
2B5
2B6
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
2
3
4
5
description
6
7
The SN74CBT16211 provides 24 bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
The device operates as a 12-bit or 24-bit bus
switch. When 1OE is low, 1A is connected to 1B.
When 2OE is low, 2A is connected to 2B.
The SN74CBT16211 is characterized for
operation from –40°C to 85°C.
V
CC
2A3
GND
2A4
2A5
2A6
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
1OE
2OE
L
1A, 1B
1A = 1B
1A = 1B
Z
2A, 2B
2A = 2B
Z
L
L
2A7 23
34 2B7
H
2A8
2A9
2A10
2A11
2A12
2B8
2B9
2B10
2B11
2B12
24
25
26
27
28
33
32
31
30
29
H
H
L
2A = 2B
Z
H
Z
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT16211
24-BIT BUS SWITCH
SCDS028E – JULY 1995 – REVISED APRIL 1997
logic diagram (positive logic)
2
54
42
1A1
1B1
14
1A12
1B12
56
15
1OE
2A1
41
29
2B1
28
2A12
2B12
55
2OE
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions
MIN
4
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
2
V
0.8
85
V
T
A
–40
°C
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT16211
24-BIT BUS SWITCH
SCDS028E – JULY 1995 – REVISED APRIL 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
10
UNIT
V
V
V
V
V
V
= 4.5 V,
= 0 V,
V
IK
CC
CC
CC
CC
CC
I
V = 5.5 V
I
I
I
µA
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 5.5 V or GND
I
±1
I
I
O
= 0,
V = V
I
or GND
3
µA
mA
pF
CC
CC
‡
∆I
CC
Control pins
Control pins
One input at 3.4 V,
Other inputs at V
or GND
2.5
CC
C
C
V = 3 V or 0
I
4.5
5.5
14
5
i
V
O
= 3 V or 0,
OE = V
CC
pF
io(OFF)
V
CC
= 4 V,
V = 2.4 V,
I
I = 15 mA
I
20
7
I = 64 mA
I
§
V = 0
I
Ω
r
on
I = 30 mA
I
5
7
V
CC
= 4.5 V
V = 2.4 V,
I
I = 15 mA
I
8
12
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
or GND.
CC
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 5 V
CC
± 0.5 V
V
= 4 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN MAX
MIN
MAX
¶
t
t
t
A or B
OE
B or A
A or B
A or B
0.25
9.3
0.25
10.1
7.1
ns
ns
ns
pd
3.9
3.3
en
OE
8.5
dis
¶
This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state resistance
of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT16211
24-BIT BUS SWITCH
SCDS028E – JULY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
S1
S1
t
Open
7 V
pd
/t
500 Ω
From Output
Under Test
t
PLZ PZL
/t
GND
t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
3 V
0 V
Output Control
(low-level
1.5 V
1.5 V
LOAD CIRCUIT
enabling)
t
t
PZL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
V
OL
+ 0.3 V
1.5 V
1.5 V
(see Note B)
V
OL
t
PHZ
t
t
PHL
PZH
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
V
OH
– 0.3 V
0 V
1.5 V
Output
1.5 V
1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 Ω, t 2.5 ns, t 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1999, Texas Instruments Incorporated
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