SN74CBT16212CDGGR [TI]

具有 –2V 下冲保护的 5V、交叉点/交换、24 通道 FET 总线开关 | DGG | 56 | -40 to 85;


型号：	SN74CBT16212CDGGR
厂家：	TEXAS INSTRUMENTS
描述：	具有 –2V 下冲保护的 5V、交叉点/交换、24 通道 FET 总线开关 \| DGG \| 56 \| -40 to 85 开关驱动光电二极管逻辑集成电路总线驱动器总线收发器
文件：	总15页 (文件大小：535K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

Member of the Texas Instruments

Widebus Family

Undershoot Protection for Off-Isolation on

A and B Ports Up To −2 V

1A1

1A2

2A1

2A2

3A1

3A2

GND

4A1

4A2

5A1

5A2

6A1

6A2

7A1

7A2

Bidirectional Data Flow, With Near-Zero

Propagation Delay

1B1

1B2

2B1

2B2

3B1

GND

3B2

4B1

4B2

5B1

5B2

6B1

6B2

7B1

7B2

8B1

GND

8B2

9B1

9B2

10B1

10B2

11B1

11B2

12B1

12B2

Low ON-State Resistance (r

)

Characteristics (r = 3 Ω Typical)

Low Input/Output Capacitance Minimizes

Loading and Signal Distortion

= 8 pF Typical)

io(OFF)

Data and Control Inputs Provide

Undershoot Clamp Diodes

Low Power Consumption

= 5 µA Max)

Operating Range From 4 V to 5.5 V

Data I/Os Support 0 to 5-V Signaling Levels

(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)

Control Inputs Can Be Driven by TTL or

5-V/3.3-V CMOS Outputs

8A1

GND

8A2

9A1

9A2

Supports Partial-Power-Down Mode

off

Operation

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

10A1

10A2

11A1

11A2

12A1

12A2

ESD Performance Tested Per JESD 22

− 2000-V Human-Body Model

(A114-B, Class II)

− 1000-V Charged-Device Model (C101)

Supports Both Digital and Analog

Applications: PCI Interface, Memory

Interleaving, Bus Isolation, Low-Distortion

Signal Gating

description/ordering information

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

Tube

SN74CBT16212CDL

SSOP − DL

CBT16212C

Tape and reel

Tube

SN74CBT16212CDLR

SN74CBT16212CDGG

SN74CBT16212CDGGR

SN74CBT16212CDGVR

−40°C to 85°C

TSSOP − DGG

TVSOP − DGV

CBT16212C

CY212C

Tape and reel

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢇ ꢉꢄ

ꢉꢃ ꢊꢅꢋ ꢆ ꢌ ꢍꢆ ꢅ ꢎꢀ ꢊꢍ ꢏꢄ ꢐꢑꢁ ꢒꢍ ꢀ ꢓꢋ ꢆ ꢄꢐ

ꢔꢊ ꢕ ꢅ ꢎ ꢀ ꢀꢓ ꢋ ꢆ ꢄꢐ ꢓ ꢋ ꢆꢐ ꢖ ꢉ ꢊꢕ ꢎꢁ ꢗꢍ ꢘꢀ ꢐ ꢙꢙ ꢆ ꢚꢘꢙ ꢆ ꢍꢄ ꢆꢋ ꢙ ꢁ

SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004

description/ordering information (continued)

The SN74CBT16212C is a high-speed TTL-compatible FET bus-exchange switch with low ON-state resistance

(r ), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the

SN74CBT16212C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring

that the switch remains in the proper OFF state.

The SN74CBT16212C operates as a 24-bit bus switch, or as a 12-bit bus-exchange that provides data

exchanging between four signal ports. The select (S0, S1, S2) inputs control the data path of the bus-exchange

switch. When the bus-exchange switch is ON, the A port is connected to the B port, allowing bidirectional data

flow between ports. When the bus-exchange switch is disabled, a high-impedance state exists between the A

and B ports.

This device is fully specified for partial-power-down applications using I . The I feature ensures that

off

damaging current will not backflow through the device when it is powered down. The device has isolation during

power off.

To ensure the high-impedance state during power up or power down, each select input should be tied to GND

through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability

of the driver.

FUNCTION TABLE

(each 12-bit bus-exchange)

INPUTS

INPUTS/OUTPUTS

FUNCTION

Disconnect

A1 port = B1 port

A1 port = B2 port

A2 port = B1 port

A2 port = B2 port

Disconnect

A1 port = B1 port

A2 port = B2 port

A1 port = B2 port

A2 port = B1 port

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004

logic diagram (positive logic)

1A1

1B1

1B2

1A2

12A1

12B1

12B2

12A2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢔꢊ ꢕ ꢅ ꢎ ꢀ ꢀꢓ ꢋ ꢆ ꢄꢐ ꢓ ꢋ ꢆꢐ ꢖ ꢉ ꢊꢕ ꢎꢁ ꢗꢍ ꢘꢀ ꢐ ꢙꢙ ꢆ ꢚꢘꢙ ꢆ ꢍꢄ ꢆꢋ ꢙ ꢁ

SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004

simplified schematic, each FET switch (SW)

Undershoot

Protection Circuit

†

EN is the internal enable signal applied to the switch.

‡

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

I/O

IK IN

I/O port clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

I/OK I/O

ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Continuous current through V

I/O

or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

Package thermal impedance, θ (see Note 5): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W

DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W

DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Storage temperature range, T

stg

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltages are with respect to ground unless otherwise specified.

2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. V and V are used to denote specific conditions for V

I/O

4. I and I are used to denote specific conditions for I .

I/O

5. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 6)

MIN

MAX

5.5

0.8

5.5

UNIT

Supply voltage

High-level control input voltage

Low-level control input voltage

Data input/output voltage

Operating free-air temperature

I/O

−40

°C

NOTE 6: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

PARAMETER

Control inputs

TEST CONDITIONS

MIN TYP

MAX

UNIT

= 4.5 V,

= 5 V,

I = −18 mA

−1.8

0 mA > I ≥ −50 mA,

Data inputs

Switch OFF

Switch OFF,

−2

IKU

= V

or GND,

Control inputs

= 5.5 V,

= 0,

= V

or GND

µA

= 0 to 5.5 V,

‡

7.5

2.5

off

V = 0,

= V or GND

V = 0

= 0 to 5.5 V,

= 0,

= V or GND,

I/O

= 5.5 V,

Switch ON or OFF

∆I

Control inputs

= 5.5 V,

One input at 3.4 V,

Other inputs at V

or GND

= 3 V or 0

= 3 V or 0,

3.5

Switch OFF,

Switch ON,

= V

or GND

io(OFF)

io(ON)

I/O

= 4 V,

V = 2.4 V,

= −15 mA

TYP at V

= 4 V

= 64 mA

= 30 mA

= −15 mA

Ω

V = 0

= 4.5 V

V = 2.4 V,

†

‡

and I refer to control inputs. V , V , I , and I refer to data pins.

All typical values are at V

= 5 V (unless otherwise noted), T = 25°C.

For I/O ports, the parameter I

includes the input leakage current.

This is the increase in supply current for each input that is at the specified voltage level, rather than V

or GND.

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by

the lower of the voltages of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 3)

= 5 V

0.5 V

= 4 V

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

MAX

MIN

MAX

A or B

B or A

0.24

0.15

6.4

1.5

pd(s)

7.2

7.7

7.5

dis

The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,

when driven by an ideal voltage source (zero output impedance).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢇ ꢉꢄ

ꢉꢃ ꢊꢅꢋ ꢆ ꢌ ꢍꢆ ꢅ ꢎꢀ ꢊꢍ ꢏꢄ ꢐꢑꢁ ꢒꢍ ꢀ ꢓꢋ ꢆ ꢄꢐ

ꢔꢊ ꢕ ꢅ ꢎ ꢀ ꢀꢓ ꢋ ꢆ ꢄꢐ ꢓ ꢋ ꢆꢐ ꢖ ꢉ ꢊꢕ ꢎꢁ ꢗꢍ ꢘꢀ ꢐ ꢙꢙ ꢆ ꢚꢘꢙ ꢆ ꢍꢄ ꢆꢋ ꢙ ꢁ

SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004

undershoot characteristics (see Figures 1 and 2)

†

PARAMETER

TEST CONDITIONS

Switch OFF,

= 5 V (unless otherwise noted), T = 25°C.

MIN

TYP

MAX

UNIT

= 5.5 V,

= V

or GND

−0.3

OUTU

†

All typical values are at V

11 V

100 kΩ

5.5 V

Input

(Open

Socket)

Input

Generator

90 %

10 %

90 %

10 %

50 Ω

2 ns 2 ns

20 ns

DUT

−2 V

100 kΩ

10 pF

Output

OUTU

)

− 0.3

Figure 1. Device Test Setup

Figure 2. Transient Input Voltage (V ) and Output

Voltage (V

) Waveforms

OUTU

(Switch OFF)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004

PARAMETER MEASUREMENT INFORMATION

Input Generator

50 Ω

TEST CIRCUIT

DUT

7 V

Open

GND

Input Generator

50 Ω

(see Note A)

∆

TEST

5 V 0.5 V

4 V

Open

500 Ω

or GND

50 pF

pd(s)

5 V 0.5 V

4 V

7 V

500 Ω

GND

50 pF

0.3 V

PLZ PZL

5 V 0.5 V

4 V

Open

500 Ω

50 pF

0.3 V

PHZ PZH

Output

Control

3 V

0 V

1.5 V

)

PLZ

PZL

Output

Waveform 1

S1 at 7 V

3.5 V

Output

Control

3 V

0 V

1.5 V

+ V

1.5 V

∆

)

(see Note B)

PZH

PHZ

PLH

PHL

Output

Waveform 2

S1 at Open

(see Note B)

− V

∆

1.5 V

Output

1.5 V

0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (t

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

)

pd(s)

C includes probe and jig capacitance.

NOTES: A.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

and t

are the same as t

PLZ

PZL

PLH

PHZ

PZH

PHL

dis

. The tpd propagation delay is the calculated RC time constant of the typical ON-state

pd(s)

resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

H. All parameters and waveforms are not applicable to all devices.

Figure 3. Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

20-Aug-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

74CBT16212CDGGRE4

74CBT16212CDGGRG4

74CBT16212CDGVRE4

74CBT16212CDGVRG4

SN74CBT16212CDGGR

SN74CBT16212CDGVR

SN74CBT16212CDL

ACTIVE

TSSOP

TVSOP

TSSOP

TVSOP

SSOP

DGG

DGV

DGG

DGV

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

SN74CBT16212CDLG4

SN74CBT16212CDLR

SN74CBT16212CDLRG4

SSOP

Green (RoHS

& no Sb/Br)

SSOP

1000

Green (RoHS

& no Sb/Br)

SSOP

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

20-Aug-2011

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74CBT16212CDGGR TSSOP

SN74CBT16212CDGVR TVSOP

DGG

DGV

2000

1000

330.0

24.4

32.4

8.6

6.8

15.6

11.7

1.8

1.6

3.1

12.0

16.0

24.0

32.0

SN74CBT16212CDLR

SSOP

11.35 18.67

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74CBT16212CDGGR

SN74CBT16212CDGVR

SN74CBT16212CDLR

TSSOP

TVSOP

SSOP

DGG

DGV

2000

1000

367.0

45.0

55.0

Pack Materials-Page 2

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

0,07

0,40

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

0,50

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001

DL (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0.025 (0,635)

0.0135 (0,343)

0.008 (0,203)

0.005 (0,13)

0.010 (0,25)

0.005 (0,13)

0.299 (7,59)

0.291 (7,39)

0.420 (10,67)

0.395 (10,03)

Gage Plane

0.010 (0,25)

0°–ā8°

0.040 (1,02)

0.020 (0,51)

Seating Plane

0.004 (0,10)

0.008 (0,20) MIN

PINS **

0.110 (2,79) MAX

0.630

DIM

0.380

(9,65)

0.730

A MAX

A MIN

(16,00) (18,54)

0.370

(9,40)

0.620

0.720

(15,75) (18,29)

4040048/E 12/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MO-118

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27

0,17

0,08

0,50

6,20

6,00

8,30

7,90

0,15 NOM

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

DIM

A MAX

12,60

12,40

14,10

13,90

17,10

16,90

A MIN

4040078/F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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