SN74CBT16213DGGR [TI]

24-BIT FET BUS-EXCHANGE SWITCH;


型号：	SN74CBT16213DGGR
厂家：	TEXAS INSTRUMENTS
描述：	24-BIT FET BUS-EXCHANGE SWITCH 光电二极管逻辑集成电路
文件：	总5页 (文件大小：85K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74CBT16213

24-BIT FET BUS-EXCHANGE SWITCH

SCDS026F – MAY 1995 – REVISED MAY 1998

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

5-Ω Switch Connection Between Two Ports

TTL-Compatible Input Levels

Package Options Include Plastic Thin

Shrink Small-Outline (DGG), Thin Very

Small-Outline (DGV), and 300-mil Shrink

Small-Outline (DL) Packages

1A1

1A2

2A1

2A2

3A1

3A2

GND

4A1

4A2

5A1

5A2

6A1

6A2

7A1

7A2

1B1

1B2

2B1

2B2

3B1

GND

3B2

4B1

4B2

5B1

5B2

6B1

6B2

7B1

7B2

8B1

GND

8B2

9B1

9B2

10B1

10B2

11B1

11B2

12B1

12B2

description

The SN74CBT16213 provides 24 bits of

high-speed TTL-compatible bus switching or

exchanging. The low on-state resistance of the

switch allows connections to be made with

minimal propagation delay.

The device operates as a 24-bit bus switch or a

12-bit bus exchanger that provides data

exchanging between the four signal ports via the

data-select (S0–S2) terminals.

The SN74CBT16213 is characterized for

operation from –40°C to 85°C.

8A1

GND

8A2

9A1

9A2

10A1

10A2

11A1

11A2

12A1

12A2

FUNCTION TABLE

INPUTS/OUTPUTS

INPUTS

FUNCTION

Disconnect

A1 port = B1 port

A1 port = B2 port

A2 port = B1 port

A2 port = B2 port

A2 and B2 A1 and B2

A1 port = A2 port = B2 port

A1 port = B1 port

A2 port = B2 port

A1 port = B2 port

A2 port = B1 port

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74CBT16213

24-BIT FET BUS-EXCHANGE SWITCH

SCDS026F – MAY 1995 – REVISED MAY 1998

logic diagram (positive logic)

1B1

1A1

1B2

1A2

12A1

12B1

12B2

12A2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74CBT16213

24-BIT FET BUS-EXCHANGE SWITCH

SCDS026F – MAY 1995 – REVISED MAY 1998

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA

Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/ W

DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W

DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 3)

MIN

MAX

UNIT

Supply voltage

5.5

High-level control input voltage

Low-level control input voltage

Operating free-air temperature

0.8

–40

°C

NOTE 3: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

‡

PARAMETER

TEST CONDITIONS

I = –18 mA

MIN TYP

MAX

–1.2

UNIT

= 4.5 V,

= 0,

V = 5.5 V

µA

= 5.5 V,

V = 5.5 V or GND

±1

= 0,

V = V

or GND

µA

∆I

Control inputs

One input at 3.4 V,

Other inputs at V

or GND

2.5

Control inputs V = 3 V or 0

4.5

8.5

B port

= 3 V or 0,

S0, S1, or S2 = V

io(OFF)

A port

= 4 V,

V = 2.4 V,

I = 15 mA

TYP at V

= 4 V

A to B or

B to A

I = 64 mA

V = 0

= 4.5 V

I = 30 mA

V = 2.4 V,

I = 15 mA

Ω

= 4 V,

V = 2.4 V,

I = 15 mA

TYP at V

= 4 V

I = 64 mA

A1 to A2

V = 0

= 4.5 V

I = 30 mA

V = 2.4 V,

I = 15 mA

‡

All typical values are at V

= 5 V (unless otherwise noted), T = 25°C.

This is the increase in supply current for each input that is at the specified TTL voltage level rather than V

or GND.

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by

the lower of the voltages of the two (A or B) terminals.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74CBT16213

24-BIT FET BUS-EXCHANGE SWITCH

SCDS026F – MAY 1995 – REVISED MAY 1998

switching characteristics over recommended operating free-air temperature range, C = 50 pF

(unless otherwise noted) (see Figure 1)

= 5 V

0.5 V

= 4 V

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

MAX

MIN

MAX

A or B

B or A

0.35

0.5

0.25

0.5

†

A or B

12.4

3.2

2.3

11.1

11.9

dis

A2 and B2

11.5

12.8

10.9

5.7

†

Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when

driven by an ideal voltage source (zero output impedance).

PARAMETER MEASUREMENT INFORMATION

7 V

TEST

Open

GND

500 Ω

Open

7 V

From Output

Under Test

PLZ PZL

Open

= 50 pF

PHZ PZH

500 Ω

(see Note A)

Output

Control

(low-level

enabling)

3 V

0 V

1.5 V

LOAD CIRCUIT

PZL

PLZ

Output

Waveform 1

S1 at 7 V

3.5 V

3 V

0 V

1.5 V

Input

+ 0.3 V

1.5 V

(see Note B)

PHZ

PHL

PLH

PZH

Output

Waveform 2

S1 at Open

(see Note B)

– 0.3 V

0 V

1.5 V

Output

1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

ENABLE AND DISABLE TIMES

NOTES: A.

C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

and t

PHL

are the same as t

dis

PLZ

PZL

PLH

PHZ

PZH

are the same as t

are the same as t .

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

SN74CBT16213DGGR [TI]

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