SN74CBT16214CDLRG4 [TI]
12-BIT 1-OF-3 FET MULTIPLEXER/DEMULTIPLEXER 5-V BUS SWITCH WITH-2-V UNDERSHOOT PROTECTION; 12位1 - OF- 3 FET多路复用器/ 5 -V BUS开关- 2 -V冲保护
| 型号： | SN74CBT16214CDLRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT 1-OF-3 FET MULTIPLEXER/DEMULTIPLEXER 5-V BUS SWITCH WITH-2-V UNDERSHOOT PROTECTION |
| 文件： | 总13页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢇ ꢉ ꢊꢅꢋ ꢆ ꢇ ꢊꢌ ꢍꢊ ꢎ ꢍ ꢏꢆ ꢐ ꢑꢒꢆ ꢋꢓ ꢒꢏ ꢔꢏꢕꢖ ꢗꢏꢐ ꢑꢒꢆꢋ ꢓ ꢒꢏ ꢔꢏ
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SCDS121B − JUNE 2003 − REVISED OCTOBER 2003
DGG OR DL PACKAGE
(TOP VIEW)
D
D
D
D
D
Member of the Texas Instruments
Widebus Family
Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
S0
1A
S1
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
S2
Bidirectional Data Flow, With Near-Zero
Propagation Delay
1B3
2A
1B1
1B2
2B1
2B2
3B1
Low ON-State Resistance (r
)
2B3
3A
on
Characteristics (r = 3 Ω Typical)
on
3B3
GND
4A
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
49 GND
48 3B2
47 4B1
46 4B2
45 5B1
(C
= 5.5 pF Typical)
io(OFF)
4B3 10
5A 11
5B3 12
6A 13
D
D
Data and Control Inputs Provide
Undershoot Clamp Diodes
Low Power Consumption
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
5B2
(I
= 3 µA Max)
CC
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
6B3
7A
6B1
D
V
Operating Range From 4 V to 5.5 V
CC
6B2
D
Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
7B3
7B1
V
7B2
CC
8A
8B1
D
D
D
D
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
GND
8B3
9A
GND
8B2
I
Supports Partial-Power-Down Mode
off
9B1
Operation
9B3
10A
10B3
11A
9B2
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
10B1
10B2
11B1
11B2
12B1
12B2
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
11B3
12A
12B3
− 1000-V Charged-Device Model (C101)
D
Supports Both Digital and Analog
Applications: PCI Interface, Bus Isolation,
Low-Distortion Signal Gating
description/ordering information
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74CBT16214CDL
SN74CBT16214CDLR
SN74CBT16214CDGG
SN74CBT16214CDGGR
SSOP − DL
CBT16214C
CBT16214C
Tape and reel
Tube
−40°C to 85°C
TSSOP − DGG
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢘꢊ ꢙ ꢅ ꢑꢀ ꢀꢚ ꢋ ꢆ ꢄ ꢛ ꢚ ꢋ ꢆꢛ ꢜ ꢉ ꢊꢙ ꢑꢁ ꢗꢏ ꢕꢀ ꢛ ꢌꢌ ꢆ ꢓꢕꢌ ꢆ ꢏꢄ ꢆꢋ ꢌ ꢁ
SCDS121B − JUNE 2003 − REVISED OCTOBER 2003
description/ordering information (continued)
The SN74CBT16214C is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state
resistance (r ), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and
on
B ports of the SN74CBT16214C provides protection for undershoot up to −2 V by sensing an undershoot event
and ensuring that the switch remains in the proper OFF state.
The SN74CBT16214C is a 12-bit 1-of-3 multiplexer/demultiplexer. The select (S0, S1, S2) inputs control the
data path of each multiplexer/demultiplexer. When the multiplexer/demultiplexer is enabled, the A port is
connected to the B port, allowing bidirectional data flow between ports. When the multiplexer/demultiplexer is
disabled, a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, each select input should be tied to GND
through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability
of the driver.
FUNCTION TABLE
INPUTS
INPUT/OUTPUT
A
FUNCTION
S2
L
S1
L
S0
L
Z
Disconnect
A port = B1 port
A port = B2 port
Disconnect
L
L
H
L
B1
B2
Z
L
H
H
L
L
H
L
H
H
H
H
Z
Disconnect
L
H
L
B3
B1
B2
A port = B3 port
A port = B1 port
A port = B2 port
H
H
H
2
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SCDS121B − JUNE 2003 − REVISED OCTOBER 2003
logic diagram (positive logic)
2
54
1B1
1A
SW
53
1B2
SW
3
1B3
SW
27
30
29
28
12A
12B1
12B2
12B3
SW
SW
SW
1
S0
56
S1
55
S2
simplified schematic, each FET switch (SW)
A
B
Undershoot
Protection Circuit
†
EN
†
EN is the internal enable signal applied to the switch.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢘꢊ ꢙ ꢅ ꢑꢀ ꢀꢚ ꢋ ꢆ ꢄ ꢛ ꢚ ꢋ ꢆꢛ ꢜ ꢉ ꢊꢙ ꢑꢁ ꢗꢏ ꢕꢀ ꢛ ꢌꢌ ꢆ ꢓꢕꢌ ꢆ ꢏꢄ ꢆꢋ ꢌ ꢁ
SCDS121B − JUNE 2003 − REVISED OCTOBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IN
I/O
IK IN
I/O port clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/OK I/O
ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Continuous current through V
I/O
or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 5): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. V and V are used to denote specific conditions for V
.
I
O
I/O
4. I and I are used to denote specific conditions for I .
I
O
I/O
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN
4
MAX
5.5
5.5
0.8
5.5
85
UNIT
V
V
V
V
V
Supply voltage
CC
High-level control input voltage
Low-level control input voltage
Data input/output voltage
Operating free-air temperature
2
V
IH
0
V
IL
0
V
I/O
T
A
−40
°C
NOTE 6: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCDS121B − JUNE 2003 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Control inputs
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
= 4.5 V,
= 5 V,
I = −18 mA
IN
−1.8
V
IK
CC
CC
CC
CC
CC
CC
CC
0 mA > I ≥ −50 mA,
I
Data inputs
Switch OFF
Switch OFF,
−2
1
V
IKU
V
V
V
= V
or GND,
IN
IN
O
CC
I
I
I
I
Control inputs
= 5.5 V,
= 5.5 V,
= 0,
= V
or GND
µA
µA
µA
µA
IN
CC
= 0 to 5.5 V,
‡
10
10
3
OZ
off
V = 0,
V
= V or GND
CC
I
IN
V = 0
V
O
= 0 to 5.5 V,
= 0,
= V or GND,
CC
I
I
V
I/O
IN
= 5.5 V,
Switch ON or OFF
CC
§
∆I
Control inputs
Control inputs
A port
V
V
= 5.5 V,
One input at 3.4 V,
Other inputs at V
CC
or GND
2.5
mA
pF
pF
pF
CC
C
C
C
= 3 V or 0
= 3 V or 0,
= 3 V or 0,
3.5
10
in
IN
V
I/O
Switch OFF,
Switch ON,
V
V
= V
= V
or GND
or GND
io(OFF)
io(ON)
IN
CC
B port
5.5
V
V
18
8
pF
I/O
IN
CC
= 4 V,
CC
V = 2.4 V,
I
O
= −15 mA
12
I
TYP at V
CC
= 4 V
¶
I
O
I
O
I
O
= 64 mA
= 30 mA
= −15 mA
3
3
5
6
6
Ω
r
on
V = 0
I
V
CC
= 4.5 V
V = 2.4 V,
I
10
V
†
‡
§
¶
and I refer to control inputs. V , V , I , and I refer to data pins.
IN
IN
I
O
I
O
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
CC
A
For I/O ports, the parameter I
includes the input leakage current.
OZ
This is the increase in supply current for each input that is at the specified voltage level, rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 3)
V
= 5 V
CC
0.5 V
V
= 4 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
#
A or B
B or A
0.24
6.7
7.2
7.5
0.15
6.3
6.6
7.3
ns
ns
ns
ns
t
t
t
t
pd
S
S
S
A
B
B
1.5
1.5
1.5
pd(s)
en
dis
#
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢇ ꢃꢄ
ꢇꢉ ꢊꢅꢋ ꢆ ꢇ ꢊꢌꢍ ꢊꢎ ꢍ ꢏ ꢆ ꢐꢑ ꢒꢆꢋ ꢓ ꢒ ꢏꢔ ꢏꢕ ꢖ ꢗꢏ ꢐ ꢑꢒꢆ ꢋꢓ ꢒꢏ ꢔꢏꢕ
ꢘꢊ ꢙ ꢅ ꢑꢀ ꢀꢚ ꢋ ꢆ ꢄ ꢛ ꢚ ꢋ ꢆꢛ ꢜ ꢉ ꢊꢙ ꢑꢁ ꢗꢏ ꢕꢀ ꢛ ꢌꢌ ꢆ ꢓꢕꢌ ꢆ ꢏꢄ ꢆꢋ ꢌ ꢁ
SCDS121B − JUNE 2003 − REVISED OCTOBER 2003
undershoot characteristics (see Figures 1 and 2)
†
PARAMETER
TEST CONDITIONS
Switch OFF,
= 5 V (unless otherwise noted), T = 25°C.
MIN
TYP
MAX
UNIT
V
V
CC
= 5.5 V,
V
IN
= V
CC
or GND
2
V
−0.3
V
OUTU
OH
†
All typical values are at V
CC
A
V
CC
11 V
100 kΩ
5.5 V
Input
(Open
Socket)
Input
Generator
90 %
10 %
90 %
10 %
50 Ω
2 ns 2 ns
20 ns
DUT
Ax
Bx
−2 V
100 kΩ
10 pF
V
S
Output
V
OH
V
OH
(V
OUTU
)
− 0.3
Figure 1. Device Test Setup
Figure 2. Transient Input Voltage (V ) and Output
I
Voltage (V
) Waveforms
OUTU
(Switch OFF)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢌ
ꢆ
ꢓ
ꢕ
ꢌ
ꢆ
ꢏ
ꢄ
ꢆ
ꢋ
ꢌ
SCDS121B − JUNE 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
7 V
Open
GND
Input Generator
50 Ω
S1
R
V
V
O
L
I
50 Ω
V
G2
C
R
L
L
(see Note A)
S1
V
I
V
∆
C
R
V
CC
TEST
L
L
5 V 0.5 V
4 V
Open
Open
500 Ω
500 Ω
V
CC
V
CC
or GND
or GND
50 pF
50 pF
t
pd(s)
5 V 0.5 V
4 V
7 V
7 V
500 Ω
500 Ω
GND
GND
50 pF
50 pF
0.3 V
0.3 V
t
/t
PLZ PZL
5 V 0.5 V
4 V
Open
Open
500 Ω
500 Ω
V
CC
V
CC
50 pF
50 pF
0.3 V
0.3 V
t
/t
PHZ PZH
Output
Control
(V
3 V
0 V
1.5 V
1.5 V
)
IN
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
Output
Control
3 V
0 V
1.5 V
V
V
+ V
1.5 V
1.5 V
OL
∆
(V
IN
)
V
OL
(see Note B)
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
− V
OH
∆
1.5 V
Output
1.5 V
1.5 V
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
C includes probe and jig capacitance.
L
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
. The tpd propagation delay is the calculated RC time constant of the typical ON-state
pd(s)
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2006
PACKAGING INFORMATION
Orderable Device
74CBT16214CDGGRE4
SN74CBT16214CDGGR
SN74CBT16214CDL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
SSOP
SSOP
SSOP
SSOP
DGG
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT16214CDLG4
SN74CBT16214CDLR
SN74CBT16214CDLRG4
DL
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Apr-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Apr-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
24
SN74CBT16214CDGGR
SN74CBT16214CDLR
DGG
DL
56
56
MLA
MLA
8.6
15.8
1.8
3.1
12
16
24
32
Q1
Q1
330
32
11.35
18.67
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74CBT16214CDGGR
SN74CBT16214CDLR
DGG
DL
56
56
MLA
MLA
333.2
336.6
333.2
342.9
31.75
41.3
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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