SN74CBT3125CDBRG4 [TI]

CBT/FST/QS/5C/B SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, GREEN, PLASTIC, SSOP-14;


型号：	SN74CBT3125CDBRG4
厂家：	TEXAS INSTRUMENTS
描述：	CBT/FST/QS/5C/B SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, GREEN, PLASTIC, SSOP-14 驱动光电二极管输出元件逻辑集成电路
文件：	总23页 (文件大小：1200K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SCDS122A − JULY 2003 − REVISED OCTOBER 2003

Undershoot Protection for Off-Isolation on

A and B Ports Up To −2 V

Control Inputs Can Be Driven by TTL or

5-V/3.3-V CMOS Outputs

Bidirectional Data Flow, With Near-Zero

Propagation Delay

Supports Partial-Power-Down Mode

off

Operation

Low ON-State Resistance (r

)

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

Characteristics (r = 3 Ω Typical)

Low Input/Output Capacitance Minimizes

Loading and Signal Distortion

ESD Performance Tested Per JESD 22

− 2000-V Human-Body Model

(A114-B, Class II)

= 5 pF Typical)

io(OFF)

− 1000-V Charged-Device Model (C101)

Data and Control Inputs Provide

Undershoot Clamp Diodes

Supports Both Digital and Analog

Applications: USB Interface, Bus Isolation,

Low-Distortion Signal Gating

Low Power Consumption

= 3 µA Max)

Operating Range From 4 V to 5.5 V

Data I/Os Support 0 to 5-V Signaling Levels

(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)

RGY PACKAGE

(TOP VIEW)

D, DB, DGV, OR PW PACKAGE

(TOP VIEW)

DBQ PACKAGE

(TOP VIEW)

4OE

3OE

1OE

2OE

1OE

2OE

4OE

3OE

13 4OE

12 4A

2OE

3OE

GND

NC − No internal connection

description/ordering information

The SN74CBT3125C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r ),

allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the

SN74CBT3125C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring

that the switch remains in the proper OFF state.

The SN74CBT3125C is organized as four 1-bit bus switches with separate output-enable (1OE, 2OE, 3OE,

4OE) inputs. It can be used as four 1-bit bus switches or as one 4-bit bus switch. When OE is low, the associated

1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports.

When OE is high, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A

and B ports.

This device is fully specified for partial-power-down applications using I . The I feature ensures that

off

damaging current will not backflow through the device when it is powered down. The device has isolation during

power off.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢄ

ꢋꢌ ꢍ ꢎꢏ ꢌ ꢐꢑ ꢒ ꢓ ꢒꢆ ꢅꢌ ꢀ ꢀ ꢔꢕ ꢆ ꢄꢖ

ꢊꢗ ꢘ ꢅ ꢌ ꢀ ꢀꢔ ꢕ ꢆ ꢄꢖ ꢔ ꢕ ꢆꢖ ꢙ ꢉ ꢗꢘ ꢌꢁ ꢎꢒ ꢏꢀ ꢖꢚ ꢚ ꢆ ꢐꢏ ꢚꢆ ꢒꢄꢆ ꢕ ꢚ ꢁ

SCDS122A − JULY 2003 − REVISED OCTOBER 2003

description/ordering information (continued)

To ensure the high-impedance state during power up or power down, OE should be tied to V

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

QFN − RGY

SOIC − D

Tape and reel SN74CBT3125CRGYR

CU125C

Tube

SN74CBT3125CD

CBT3125C

Tape and reel

Tube

SN74CBT3125CDR

SN74CBT3125CDB

SN74CBT3125CDBR

SN74CBT3125CDBQR

SN74CBT3125CPW

SN74CBT3125CPWR

SN74CBT3125CDGVR

SSOP − DB

CU125C

−40°C to 85°C

Tape and reel

SSOP (QSOP) − DBQ Tape and reel

Tube

TSSOP − PW

CU125C

Tape and reel

TVSOP − DGV

Tape and reel

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each bus switch)

INPUT INPUT/OUTPUT

FUNCTION

A port = B port

Disconnect

logic diagram (positive logic)

1OE

2OE

4OE

3OE

Pin numbers shown are for the D, DB, DGV, PW, and RGY packages.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCDS122A − JULY 2003 − REVISED OCTOBER 2003

simplified schematic, each FET switch (SW)

Undershoot

Protection Circuit

†

EN is the internal enable signal applied to the switch.

‡

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

I/O

IK IN

I/O port clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

I/OK I/O

ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Continuous current through V

I/O

or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

Package thermal impedance, θ (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W

(see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W

(see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W

(see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W

(see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W

(see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltages are with respect to ground unless otherwise specified.

2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. V and V are used to denote specific conditions for V

I/O

4. I and I are used to denote specific conditions for I .

I/O

5. The package thermal impedance is calculated in accordance with JESD 51-7.

6. The package thermal impedance is calculated in accordance with JESD 51-5.

recommended operating conditions (see Note 7)

MIN

MAX

5.5

0.8

5.5

UNIT

Supply voltage

High-level control input voltage

Low-level control input voltage

Data input/output voltage

Operating free-air temperature

I/O

−40

°C

NOTE 7: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢋꢌ ꢍ ꢎꢏ ꢌ ꢐꢑ ꢒ ꢓ ꢒꢆ ꢅꢌ ꢀ ꢀ ꢔꢕ ꢆ ꢄꢖ

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SCDS122A − JULY 2003 − REVISED OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

PARAMETER

Control inputs

TEST CONDITIONS

MIN TYP

MAX

UNIT

= 4.5 V,

= 5 V,

I = −18 mA

−1.8

0 mA > I ≥ −50 mA,

Data inputs

Switch OFF

Switch OFF,

−2

IKU

= V

or GND,

Control inputs

= 5.5 V,

= 0,

= V

or GND

µA

= 0 to 5.5 V,

‡

off

V = 0,

= V or GND

V = 0

= 0 to 5.5 V,

= 0,

= V or GND,

I/O

= 5.5 V,

Switch ON or OFF

∆I

Control inputs

= 5.5 V,

One input at 3.4 V,

Other inputs at V

or GND

2.5

= 3 V or 0

= 3 V or 0,

Switch OFF,

Switch ON,

= V

or GND

io(OFF)

io(ON)

I/O

12.5

= 4 V,

V = 2.4 V,

= −15 mA

TYP at V

= 4 V

= 64 mA

= 30 mA

= −15 mA

Ω

V = 0

= 4.5 V

V = 2.4 V,

†

‡

and I refer to control inputs. V , V , I , and I refer to data pins.

All typical values are at V

= 5 V (unless otherwise noted), T = 25°C.

For I/O ports, the parameter I

includes the input leakage current.

This is the increase in supply current for each input that is at the specified voltage level, rather than V

or GND.

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by

the lower of the voltages of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 3)

= 5 V

0.5 V

= 4 V

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

MAX

MIN

MAX

A or B

B or A

A or B

0.24

4.4

0.15

1.5

4.4

dis

The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,

when driven by an ideal voltage source (zero output impedance).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCDS122A − JULY 2003 − REVISED OCTOBER 2003

undershoot characteristics (see Figures 1 and 2)

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

= 5.5 V,

Switch OFF,

= V

or GND

−0.3

OUTU

†

All typical values are at V

= 5 V (unless otherwise noted), T = 25°C.

11 V

100 kΩ

5.5 V

Input

(Open

Socket)

Input

Generator

90 %

10 %

90 %

10 %

50 Ω

2 ns 2 ns

20 ns

DUT

−2 V

100 kΩ

10 pF

Output

OUTU

)

− 0.3

Figure 1. Device Test Setup

Figure 2. Transient Input Voltage (V ) and Output

Voltage (V

) Waveforms

OUTU

(Switch OFF)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢄ

ꢋꢌ ꢍ ꢎꢏ ꢌ ꢐꢑ ꢒ ꢓ ꢒꢆ ꢅꢌ ꢀ ꢀ ꢔꢕ ꢆ ꢄꢖ

ꢊꢗ ꢘ ꢅ ꢌ ꢀ ꢀꢔ ꢕ ꢆ ꢄꢖ ꢔ ꢕ ꢆꢖ ꢙ ꢉ ꢗꢘ ꢌꢁ ꢎꢒ ꢏꢀ ꢖꢚ ꢚ ꢆ ꢐꢏ ꢚꢆ ꢒꢄꢆ ꢕ ꢚ ꢁ

SCDS122A − JULY 2003 − REVISED OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION

Input Generator

50 Ω

TEST CIRCUIT

DUT

7 V

Open

GND

Input Generator

50 Ω

(see Note A)

∆

TEST

5 V 0.5 V

4 V

Open

500 Ω

or GND

50 pF

pd(s)

5 V 0.5 V

4 V

7 V

500 Ω

GND

50 pF

0.3 V

PLZ PZL

5 V 0.5 V

4 V

Open

500 Ω

50 pF

0.3 V

PHZ PZH

Output

Control

3 V

0 V

1.5 V

)

PLZ

PZL

Output

Waveform 1

S1 at 7 V

3.5 V

Output

Control

3 V

0 V

1.5 V

+ V

1.5 V

∆

)

(see Note B)

PZH

PHZ

PLH

PHL

Output

Waveform 2

S1 at Open

(see Note B)

− V

∆

1.5 V

Output

1.5 V

0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (t

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

)

pd(s)

C includes probe and jig capacitance.

NOTES: A.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

and t

are the same as t

PLZ

PZL

PLH

PHZ

PZH

PHL

dis

. The tpd propagation delay is the calculated RC time constant of the typical ON-state

pd(s)

resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

H. All parameters and waveforms are not applicable to all devices.

Figure 3. Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

26-Aug-2013

PACKAGING INFORMATION

Orderable Device

SN74CBT3125CD

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

ACTIVE

SOIC

SSOP

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

CBT3125C

SN74CBT3125CDBQR

SN74CBT3125CDBQRE4

SN74CBT3125CDBQRG4

SN74CBT3125CDBR

SN74CBT3125CDBRE4

SN74CBT3125CDBRG4

SN74CBT3125CDE4

SN74CBT3125CDG4

ACTIVE

DBQ

2500

2000

Green (RoHS

& no Sb/Br)

CU125C

CBT3125C

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

SN74CBT3125CDGVRE4

SN74CBT3125CDGVRG4

SN74CBT3125CDR

ACTIVE

TVSOP

SOIC

DGV

TBD

Call TI

-40 to 85

CU125C

CBT3125C

TBD

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

SN74CBT3125CDRE4

SN74CBT3125CDRG4

SN74CBT3125CPW

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

CBT3125C

CU125C

Green (RoHS

& no Sb/Br)

TSSOP

Green (RoHS

& no Sb/Br)

SN74CBT3125CPWE4

SN74CBT3125CPWG4

Green (RoHS

& no Sb/Br)

CU125C

Green (RoHS

& no Sb/Br)

CU125C

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

26-Aug-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

SN74CBT3125CPWR

SN74CBT3125CPWRE4

SN74CBT3125CPWRG4

SN74CBT3125CRGYR

SN74CBT3125CRGYRG4

ACTIVE

TSSOP

VQFN

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

CU125C

ACTIVE

2000

3000

Green (RoHS

& no Sb/Br)

-40 to 85

CU125C

Green (RoHS

& no Sb/Br)

-40 to 85

RGY

Green (RoHS

& no Sb/Br)

-40 to 85

VQFN

Green (RoHS

& no Sb/Br)

-40 to 85

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

26-Aug-2013

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Aug-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74CBT3125CDBR

SN74CBT3125CDR

SN74CBT3125CPWR

SN74CBT3125CRGYR

SSOP

SOIC

2000

2500

2000

3000

330.0

16.4

12.4

8.2

6.5

6.6

9.0

2.5

2.1

12.0

8.0

16.0

12.0

TSSOP

VQFN

RGY

6.9

5.6

1.6

3.75

1.15

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Aug-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74CBT3125CDBR

SN74CBT3125CDR

SN74CBT3125CPWR

SN74CBT3125CRGYR

SSOP

SOIC

2000

2500

2000

3000

367.0

333.2

367.0

345.9

367.0

38.0

28.6

35.0

TSSOP

VQFN

RGY

Pack Materials-Page 2

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

0,07

0,40

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

0,50

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

0,15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

0,25

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

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SN74CBT3125CDBRG4 [TI]

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