SN74CBT3126DBRG4 [TI]
QUADRUPLE FET BUS SWITCH; 四路FET总线开关
| 型号： | SN74CBT3126DBRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE FET BUS SWITCH |
| 文件： | 总19页 (文件大小：1133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020K − MAY 1995 − REVISED OCTOBER 2003
D
D
Standard ’126-Type Pinout (D, DB, DGV,
and PW Packages)
D
D
TTL-Compatible Input Levels
Latch-Up Performance Exceeds 250 mA Per
JESD 17
5-Ω Switch Connection Between Two Ports
D, DB, DGV, OR PW PACKAGE
(TOP VIEW)
DBQ PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1OE
1A
1B
2OE
2A
2B
VCC
1
2
3
4
5
6
7
14
VCC
15 4OE
14 4A
13 4B
12 3OE
NC
1OE
1A
1B
2OE
2A
1
2
3
4
5
6
7
8
16
13 4OE
12 4A
11 4B
1
14
1A
1B
2OE
2A
13 4OE
12 4A
2
3
4
5
6
10
9
3OE
3A
3B
11
10
9
4B
3OE
3A
11
10
9
3A
3B
NC
8
GND
2B
GND
2B
7
8
NC − No internal connection
description/ordering information
The SN74CBT3126 quadruple FET bus switch features independent line switches. Each switch is disabled
when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
QFN − RGY
Tape and reel
SN74CBT3126RGYR
SN74CBT3126D
CU126
Tube
SOIC − D
CBT3126
Tape and reel
Tape and reel
SN74CBT3126DR
SN74CBT3126DBR
SN74CBT3126DBQR
SN74CBT3126PW
SN74CBT3126PWR
SN74CBT3126DGVR
SSOP − DB
CU126
CU126
−40°C to 85°C
SSOP (QSOP) − DBQ Tape and reel
Tube
TSSOP − PW
Tape and reel
CU126
CU126
TVSOP − DGV
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each bus switch)
INPUT
FUNCTION
OE
L
Disconnect
A = B
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020K − MAY 1995 − REVISED OCTOBER 2003
logic diagram (positive logic)
2
3
1A
1B
2B
3B
1
5
1OE
2A
6
8
4
9
2OE
3A
10
12
3OE
4A
11
4B
13
4OE
Pin numbers shown are for the D, DB, DGV, PW, and RGY packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
K
I/O
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
MIN
4
MAX
UNIT
V
V
V
V
T
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
2
V
0.8
85
V
−40
°C
A
NOTE 4: All unused control inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020K − MAY 1995 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
−1.2
1
UNIT
V
V
V
V
V
V
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
I = −18 mA
IK
CC
CC
CC
CC
I
I
I
V = 5.5 V or GND
μA
μA
mA
pF
I
I
I
O
= 0,
V = V or GND
I
3
CC
CC
‡
ΔI
Control inputs
One input at 3.4 V,
Other inputs at V or GND
2.5
CC
CC
C
C
Control inputs V = 3 V or 0
3
i
I
V
V
= 3 V or 0,
OE = GND
4
16
5
pF
io(OFF)
O
= 4 V,
TYP at V = 4 V,
V = 2.4 V,
I
I = 15 mA
I
22
7
CC
CC
I = 64 mA
I
§
Ω
r
V = 0
on
I
V
CC
= 4.5 V
I = 30 mA
I
5
7
V = 2.4 V,
I
I = 15 mA
I
10
15
†
‡
§
All typical values are at V = 5 V (unless otherwise noted), T = 25°C.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V or GND.
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
CC
A
CC
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
V
= 5 V
0.5 V
CC
V
= 4 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
¶
t
A or B
B or A
0.35
0.25
ns
pd
t
t
OE
OE
A or B
A or B
5.4
5
1.6
1
5.1
4.5
ns
ns
en
dis
¶
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3126
QUADRUPLE FET BUS SWITCH
SCDS020K − MAY 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
TEST
S1
S1
500 Ω
t
Open
7 V
From Output
Under Test
pd
t
/t
PLZ PZL
t
/t
Open
PHZ PZH
C = 50 pF
(see Note A)
L
500 Ω
3 V
0 V
Output
Control
1.5 V
1.5 V
LOAD CIRCUIT
t
t
t
PLZ
PZL
PZH
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
V
V
+ 0.3 V
1.5 V
1.5 V
OL
V
OL
(see Note B)
t
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
− 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
dis
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
SN74CBT3126D
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
SOIC
D
14
16
16
16
14
14
14
14
14
14
14
14
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CBT3126
SN74CBT3126DBQR
SN74CBT3126DBQRE4
SN74CBT3126DBQRG4
SN74CBT3126DBR
SN74CBT3126DBRE4
SN74CBT3126DBRG4
SN74CBT3126DE4
SN74CBT3126DG4
SN74CBT3126DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBQ
DBQ
DBQ
DB
DB
DB
D
2500
2500
2500
2000
2000
2000
50
Green (RoHS
& no Sb/Br)
CU126
Green (RoHS
& no Sb/Br)
CU126
Green (RoHS
& no Sb/Br)
CU126
Green (RoHS
& no Sb/Br)
CU126
Green (RoHS
& no Sb/Br)
CU126
Green (RoHS
& no Sb/Br)
CU126
Green (RoHS
& no Sb/Br)
CBT3126
CBT3126
CBT3126
CBT3126
CBT3126
CU126
SOIC
D
50
Green (RoHS
& no Sb/Br)
SOIC
D
2500
2500
2500
90
Green (RoHS
& no Sb/Br)
SN74CBT3126DRE4
SN74CBT3126DRG4
SN74CBT3126PW
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
Green (RoHS
& no Sb/Br)
SN74CBT3126PWE4
SN74CBT3126PWG4
SN74CBT3126PWR
SN74CBT3126PWRE4
90
Green (RoHS
& no Sb/Br)
CU126
90
Green (RoHS
& no Sb/Br)
CU126
2000
2000
Green (RoHS
& no Sb/Br)
CU126
Green (RoHS
& no Sb/Br)
CU126
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
SN74CBT3126PWRG4
SN74CBT3126RGYR
SN74CBT3126RGYRG4
ACTIVE
TSSOP
VQFN
VQFN
PW
14
14
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
CU126
ACTIVE
ACTIVE
RGY
RGY
3000
3000
Green (RoHS
& no Sb/Br)
-40 to 85
CU126
CU126
Green (RoHS
& no Sb/Br)
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74CBT3126DBR
SN74CBT3126DR
SSOP
SOIC
DB
D
14
14
14
14
2000
2500
2000
3000
330.0
330.0
330.0
330.0
16.4
16.4
12.4
12.4
8.2
6.5
6.6
9.0
2.5
2.1
12.0
8.0
8.0
8.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
SN74CBT3126PWR
SN74CBT3126RGYR
TSSOP
VQFN
PW
RGY
6.9
5.6
1.6
3.75
3.75
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74CBT3126DBR
SN74CBT3126DR
SSOP
SOIC
DB
D
14
14
14
14
2000
2500
2000
3000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
35.0
35.0
SN74CBT3126PWR
SN74CBT3126RGYR
TSSOP
VQFN
PW
RGY
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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