SN74CBT3244PWG4 [TI]
CBT/FST/QS/5C/B SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, TSSOP-20;
| 型号： | SN74CBT3244PWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CBT/FST/QS/5C/B SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, TSSOP-20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总21页 (文件大小：1189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBT3244
OCTAL FET BUS SWITCH
SCDS001N − NOVEMBER 1992 − REVISED SEPTEMBER 2003
D
D
Standard ’244-Type Pinout
D
TTL-Compatible Input Levels
5-Ω Switch Connection Between Two Ports
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
2OE
1B1
2A4
1B2
2A3
1B3
2A2
1B4
2A1
1OE
1A1
2B4
1A2
2B3
1A3
2B2
1A4
2B1
GND
1
20
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
1A1
2B4
1A2
2B3
1A3
2B2
1A4
2B1
2OE
1B1
2A4
1B2
2A3
1B3
2A2
1B4
10
11
GQN OR ZQN PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
1
2
3
4
A
B
C
D
E
A
B
C
D
E
1A1
1A2
1A3
1A4
GND
1OE
2A4
2B3
2A2
2B1
V
2OE
1B1
1B2
1B3
1B4
CC
2B4
2A3
2B2
2A1
description/ordering information
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
T
PACKAGE
A
PART NUMBER
SN74CBT3244RGYR
SN74CBT3244DW
SN74CBT3244DWR
SN74CBT3244DBR
SN74CBT3244DBQR
SN74CBT3244PW
SN74CBT3244PWR
SN74CBT3244DGVR
SN74CBT3244GQNR
SN74CBT3244ZQNR
QFN − RGY
Tape and reel
Tube
CU244
SOIC − DW
SSOP − DB
CBT3244
Tape and reel
Tape and reel
Tape and reel
Tube
CU244
SSOP (QSOP) − DBQ
CBT3244
−40°C to 85°C
TSSOP − PW
CU244
CU244
Tape and reel
Tape and reel
TVSOP − DGV
VFBGA − GQN
Tape and reel
CU244
VFBGA − ZQN (Pb-free)
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3244
OCTAL FET BUS SWITCH
SCDS001N − NOVEMBER 1992 − REVISED SEPTEMBER 2003
description/ordering information (continued)
The SN74CBT3244 provides eight bits of high-speed TTL-compatible bus switching. The SOIC, SSOP, TSSOP,
and TVSOP packages provide a standard ’244 device pinout. The low on-state resistance of the switch allows
connections to be made with minimal propagation delay.
The device is organized as two 4-bit low-impedance switches with separate output-enable (OE) inputs. When
OE is low, the switch is on, and data can flow from port A to port B, or vice versa. When OE is high, the switch
is open, and the high-impedance state exists between the two ports.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each 4-bit bus switch)
INPUT
FUNCTION
OE
L
A port = B port
Disconnect
H
logic diagram (positive logic)
2
8
18
12
1A1
1A4
1B1
1B4
1
1OE
2A1
11
9
3
2B1
2B4
17
19
2A4
2OE
Pin numbers shown are for the DB, DBQ, DGV, DW, RGY, and PW packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3244
OCTAL FET BUS SWITCH
SCDS001N − NOVEMBER 1992 − REVISED SEPTEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
K
I/O
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
(see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
(see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
(see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 2): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
MIN
4.5
2
MAX
UNIT
V
V
V
V
T
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
V
0.8
85
V
−40
°C
A
NOTE 4: All unused control inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
−1.2
5
UNIT
V
V
IK
V
V
V
V
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
I = −18 mA
CC
CC
CC
CC
I
I
I
V = 5.5 V or GND
μA
μA
mA
pF
I
I
I
O
= 0,
V = V or GND
I
50
CC
CC
§
ΔI
CC
Control inputs
Control inputs
One input at 3.4 V,
Other inputs at V or GND
3.5
CC
C
C
V = 3 V or 0
I
3
i
V
= 3 V or 0,
OE = V
CC
6
5
pF
io(OFF)
O
I = 64 mA
7
7
I
V = 0
I
¶
V
CC
= 4.5 V
I = 30 mA
I
5
Ω
r
on
V = 2.4 V,
I
I = 15 mA
I
10
15
‡
§
¶
All typical values are at V = 5 V, T = 25°C.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V or GND.
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lowest voltage of the two (A or B) terminals.
CC
A
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3244
OCTAL FET BUS SWITCH
SCDS001N − NOVEMBER 1992 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
†
t
A or B
OE
B or A
A or B
A or B
0.25
8.9
ns
ns
ns
pd
t
en
1
1
t
dis
7.4
OE
†
This propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
7 V
TEST
S1
S1
Open
GND
500 Ω
t
Open
7 V
From Output
Under Test
pd
t
/t
PLZ PZL
t
/t
Open
PHZ PZH
C = 50 pF
(see Note A)
L
500 Ω
3 V
0 V
Output
Control
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V + 0.3 V
OL
V
OL
(see Note B)
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
V
OH
− 0.3 V
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
dis
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
SN74CBT3244DBLE
SN74CBT3244DBQR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
20
20
TBD
Call TI
Call TI
-40 to 85
-40 to 85
DBQ
2500
2500
2500
2000
2000
2000
2000
2000
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CBT3244
SN74CBT3244DBQRE4
SN74CBT3244DBQRG4
SN74CBT3244DBR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SSOP
TVSOP
TVSOP
TVSOP
SOIC
DBQ
DBQ
DB
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
CBT3244
CBT3244
CU244
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74CBT3244DBRG4
SN74CBT3244DGVR
SN74CBT3244DGVRE4
SN74CBT3244DGVRG4
SN74CBT3244DW
DB
Green (RoHS
& no Sb/Br)
CU244
DGV
DGV
DGV
DW
DW
DW
DW
DW
DW
PW
Green (RoHS
& no Sb/Br)
CU244
Green (RoHS
& no Sb/Br)
CU244
Green (RoHS
& no Sb/Br)
CU244
Green (RoHS
& no Sb/Br)
CBT3244
CBT3244
CBT3244
CBT3244
CBT3244
CBT3244
CU244
SN74CBT3244DWE4
SN74CBT3244DWG4
SN74CBT3244DWR
SN74CBT3244DWRE4
SN74CBT3244DWRG4
SN74CBT3244PW
SOIC
25
Green (RoHS
& no Sb/Br)
SOIC
25
Green (RoHS
& no Sb/Br)
SOIC
2000
2000
2000
70
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
SN74CBT3244PWE4
PW
70
Green (RoHS
& no Sb/Br)
CU244
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
SN74CBT3244PWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CU244
SN74CBT3244PWLE
SN74CBT3244PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
20
20
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
3000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CU244
CU244
CU244
CU244
CU244
SN74CBT3244PWRE4
SN74CBT3244PWRG4
SN74CBT3244RGYR
SN74CBT3244RGYRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
VQFN
PW
PW
20
20
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
RGY
RGY
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74CBT3244DBQR
SN74CBT3244DBR
SN74CBT3244DGVR
SN74CBT3244DWR
SN74CBT3244PWR
SN74CBT3244RGYR
SSOP
SSOP
TVSOP
SOIC
DBQ
DB
20
20
20
20
20
20
2500
2000
2000
2000
2000
3000
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
12.4
24.4
16.4
12.4
6.5
8.2
9.0
7.5
5.6
13.0
7.1
4.8
2.1
2.5
1.6
2.7
1.6
1.6
8.0
12.0
8.0
16.0
16.0
12.0
24.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
DGV
DW
6.9
10.8
6.95
3.8
12.0
8.0
TSSOP
VQFN
PW
RGY
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74CBT3244DBQR
SN74CBT3244DBR
SN74CBT3244DGVR
SN74CBT3244DWR
SN74CBT3244PWR
SN74CBT3244RGYR
SSOP
SSOP
TVSOP
SOIC
DBQ
DB
20
20
20
20
20
20
2500
2000
2000
2000
2000
3000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
35.0
45.0
38.0
35.0
DGV
DW
TSSOP
VQFN
PW
RGY
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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