SN74CBT3253CPWE4 [TI]
CBT/FST/QS/5C/B SERIES, DUAL 1 LINE TO 4 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, TSSOP-16;
| 型号： | SN74CBT3253CPWE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CBT/FST/QS/5C/B SERIES, DUAL 1 LINE TO 4 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, TSSOP-16 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总21页 (文件大小：929K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBT3253C
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION
www.ti.com
SCDS123B–JULY 2003–REVISED JANUARY 2007
FEATURES
•
•
•
•
•
SN74CBT3253C Functionally Identical to
Industry-Standard ’3253 Function
Undershoot Protection for Off-Isolation on A
and B Ports up to –2 V
Bidirectional Data Flow, With Near-Zero
Propagation Delay
Low ON-State Resistance (ron) Characteristics
(ron = 3 Ω Typical)
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 5.5 pF Typical)
•
Data and Control Inputs Provide Undershoot
Clamp Diodes
•
•
•
Low Power Consumption (ICC = 3 µA Max)
VCC Operating Range From 4 V to 5.5 V
Data I/Os Support 0 to 5-V Signaling Levels
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
•
•
•
•
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
–
2000-V Human-Body Model
(A114-B, Class II)
–
1000-V Charged-Device Model (C101)
•
•
Supports I2C Bus Expansion
Supports Both Digital and Analog
Applications: USB Interface, Bus Isolation,
Low-Distortion Signal Gating
DESCRIPTION/ORDERING INFORMATION
The SN74CBT3253C is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state
resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B
ports of the SN74CBT3253C provides protection for undershoot up to –2 V by sensing an undershoot event and
ensuring that the switch remains in the proper OFF state.
The SN74CBT3253C is organized as two 1-of-4 multiplexer/demultiplexers with separate output-enable (1OE,
2OE) inputs. The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. When OE is low,
the associated multiplexer/demultiplexer is enabled, and the A port is connected to the B port, allowing
bidirectional data flow between ports. When OE is high, the associated multiplexer/demultiplexer is disabled, and
a high-impedance state exists between the A and B ports.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74CBT3253C
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION
www.ti.com
SCDS123B–JULY 2003–REVISED JANUARY 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging
current will not backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74CBT3253CRGYR
SN74CBT3253CD
TOP-SIDE MARKING
CU253C
QFN – RGY
SOIC – D
Reel of 1000
Tube of 40
Reel of 2500
Tube of 80
Reel of 2000
CBT3253C
SN74CBT3253CDR
SN74CBT3253CDB
–40°C to 85°C
SSOP – DB
CU253C
CU253C
CU253C
SN74CBT3253CDBR
SN74CBT3253CDBQR
SN74CBT3253CPW
SN74CBT3253CPWR
SSOP (QSOP) – DBQ Reel of 2500
Tube of 90
TSSOP – PW
Reel of 2000
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(each multiplexer/demultiplexer)
INPUTS
INPUT/OUTPUT
A
FUNCTION
OE
L
S1
L
S0
L
B1
B2
B3
B4
X
A port = B1 port
A port = B2 port
A port = B3 port
A port = B4 port
Disconnect
L
L
H
L
L
H
H
X
L
H
X
H
2
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SN74CBT3253C
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION
www.ti.com
SCDS123B–JULY 2003–REVISED JANUARY 2007
LOGIC DIAGRAM (POSITIVE LOGIC)
7
6
1A
1B1
1B2
1B3
1B4
SW
5
4
3
SW
SW
SW
9
10
11
12
13
2A
2B1
2B2
2B3
2B4
SW
SW
SW
SW
14
2
S0
S1
1
1OE
2OE
15
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
EN(1)
(1) EN is the internal enable signal applied to the switch.
3
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SN74CBT3253C
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION
www.ti.com
SCDS123B–JULY 2003–REVISED JANUARY 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VIN
VI/O
IIK
Supply voltage
7
7
V
Control input voltage range(2)(3)
Switch I/O voltage range(2)(3)(4)
Control input clamp current
I/O port clamp current
V
7
V
VIN < 0
VI/O < 0
–50
–50
±128
±100
73
mA
mA
mA
mA
II/OK
II/O
ON-state switch current(5)
Continuous current through VCC or GND terminals
D package(6)
DB package(6)
DBQ package(6)
PW package(6)
RGY package(7)
82
θJA
Package thermal impedance
Storage temperature range
90 °C/W
108
39
Tstg
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VI and VO are used to denote specific conditions for VI/O
(5) II and IO are used to denote specific conditions for II/O
.
.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
(7) The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions(1)
MIN
4
MAX
5.5
5.5
0.8
5.5
85
UNIT
V
VCC
VIH
VIL
Supply voltage
High-level control input voltage
Low-level control input voltage
Data input/output voltage
Operating free-air temperature
2
V
0
V
VI/O
TA
0
V
–40
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SN74CBT3253C
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION
www.ti.com
SCDS123B–JULY 2003–REVISED JANUARY 2007
Electrical Characteristics(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Control inputs
TEST CONDITIONS
IIN = –18 mA
MIN TYP(2)
MAX UNIT
VIK
VIKU
IIN
VCC = 4.5 V,
VCC = 5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 0,
–1.8
V
0 mA > II ≥ –50 mA,
VIN = VCC or GND,
Data inputs
Switch OFF
–2
V
Control inputs
VIN = VCC or GND
±1
µA
µA
µA
µA
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC or GND
(3)
IOZ
Ioff
±10
10
VO = 0 to 5.5 V,
VI = 0
II/O = 0,
VIN = VCC or GND,
ICC
VCC = 5.5 V,
Switch ON or OFF
Other inputs at VCC or GND
3
(4)
∆ICC
Control inputs
Control inputs
A port
VCC = 5.5 V,
One input at 3.4 V,
2.5
mA
pF
Cin
VIN = 3 V or 0
3.5
14
Cio(OFF)
Cio(ON)
VI/O = 3 V or 0,
Switch OFF,
VIN = VCC or GND
pF
pF
B port
5.5
22
VI/O = 3 V or 0,
Switch ON,
VI = 2.4 V,
VIN = VCC or GND
IO = –15 mA
VCC = 4 V,
TYP at VCC = 4 V
8
12
(5)
IO = 64 mA
IO = 30 mA
IO = –15 mA
3
3
5
6
6
ron
Ω
VI = 0
VCC = 4.5 V
VI = 2.4 V,
10
(1) VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
(2) All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND
(5) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 3)
VCC = 5 V
± 0.5 V
VCC = 4 V
MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
0.15
5.4
(1)
tpd
A or B
S
B or A
A
0.24
5.9
6.2
5.7
6.2
5.7
ns
ns
tpd(s)
ten
1.5
1.5
1.5
1.5
1.5
S
B
5.8
ns
ns
OE
S
A or B
B
5.3
5.8
tdis
OE
A or B
5.3
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
5
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SN74CBT3253C
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION
www.ti.com
SCDS123B–JULY 2003–REVISED JANUARY 2007
Undershoot Characteristics
See Figure 1 and Figure 2
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
VOUTU
VCC = 5.5 V,
Switch OFF,
VIN = VCC or GND
2
VOH – 0.3
V
(1) All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
100 kΩ
50 Ω
100 kΩ
Figure 1. Device Test Setup
Figure 2. Transient Input Voltage (VI) and
Output Voltage (VOUTU) Waveforms
(Switch OFF)
6
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SN74CBT3253C
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION
www.ti.com
SCDS123B–JULY 2003–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
7 V
Open
GND
Input Generator
50 Ω
S1
R
L
V
I
V
O
50 Ω
V
G2
C
L
R
L
(see Note A)
S1
V
I
C
L
V
∆
R
L
V
CC
TEST
5 V ± 0.5 V
Open
Open
500 Ω
500 Ω
V
V
or GND
or GND
50 pF
50 pF
CC
t
pd(s)
4 V
CC
5 V ± 0.5 V
7 V
7 V
500 Ω
500 Ω
GND
GND
50 pF
50 pF
0.3 V
0.3 V
t
/t
PLZ PZL
4 V
5 V ± 0.5 V
Open
Open
500 Ω
500 Ω
V
V
50 pF
50 pF
0.3 V
0.3 V
CC
t
/t
PHZ PZH
4 V
CC
Output
Control
(V
3 V
0 V
1.5 V
1.5 V
)
IN
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
Output
Control
3 V
0 V
1.5 V
V
V
+ V
∆
1.5 V
1.5 V
OL
(V
IN
)
V
OL
(see Note B)
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
− V
∆
OH
1.5 V
Output
1.5 V
1.5 V
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
en
are the same as t
. The t propagation delay is the calculated RC time constant of the typical ON-state resistance
pd(s) pd
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
7
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74CBT3253CD
SN74CBT3253CDBQR
SN74CBT3253CDBQRE4
SN74CBT3253CDBQRG4
SN74CBT3253CDBR
SN74CBT3253CDBRE4
SN74CBT3253CDBRG4
SN74CBT3253CDE4
SN74CBT3253CDG4
SN74CBT3253CDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
SOIC
D
DBQ
DBQ
DBQ
DB
DB
DB
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
2500
2500
2500
2000
2000
2000
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SOIC
D
40
Green (RoHS
& no Sb/Br)
SOIC
D
2500
2500
2500
90
Green (RoHS
& no Sb/Br)
SN74CBT3253CDRE4
SN74CBT3253CDRG4
SN74CBT3253CPW
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
Green (RoHS
& no Sb/Br)
SN74CBT3253CPWE4
SN74CBT3253CPWG4
SN74CBT3253CPWR
SN74CBT3253CPWRE4
90
Green (RoHS
& no Sb/Br)
90
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
Status (1)
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74CBT3253CPWRG4
SN74CBT3253CRGYR
SN74CBT3253CRGYRG4
TSSOP
VQFN
VQFN
PW
RGY
RGY
16
16
16
2000
3000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74CBT3253CDBR
SN74CBT3253CDR
SN74CBT3253CPWR
SN74CBT3253CRGYR
SSOP
SOIC
DB
D
16
16
16
16
2000
2500
2000
3000
330.0
330.0
330.0
330.0
16.4
16.4
12.4
12.4
8.2
6.5
6.9
3.8
6.6
10.3
5.6
2.5
2.1
1.6
1.5
12.0
8.0
8.0
8.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
TSSOP
VQFN
PW
RGY
4.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74CBT3253CDBR
SN74CBT3253CDR
SN74CBT3253CPWR
SN74CBT3253CRGYR
SSOP
SOIC
DB
D
16
16
16
16
2000
2500
2000
3000
367.0
333.2
367.0
367.0
367.0
345.9
367.0
367.0
38.0
28.6
35.0
35.0
TSSOP
VQFN
PW
RGY
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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