SN74CBT3390DW [TI]
CBT/FST/QS/5C/B SERIES, OCTAL MULTIPLEXER AND DEMUX/DECODER, PDSO28, SO-28;
| 型号： | SN74CBT3390DW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CBT/FST/QS/5C/B SERIES, OCTAL MULTIPLEXER AND DEMUX/DECODER, PDSO28, SO-28 光电二极管 |
| 文件： | 总4页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBT3390
8-BIT TO 16-BIT FET MULTIPLEXER/DEMULTIPLEXER BUS SWITCH
SCDS071 – JULY 1998
DL OR DW PACKAGE
D
D
D
5-Ω Switch Connection Between Two Ports
(TOP VIEW)
TTL-Compatible Input Levels
Package Options Include Plastic Shrink
Small-Outline (DL) and Small-Outline (DW)
Packages
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1B1
2B1
A1
1B2
2B2
A2
1B3
2B3
A3
1B4
2B4
A4
V
CC
2
1B8
2B8
A8
1B7
2B7
A7
1B6
2B6
A6
1B5
2B5
A5
3
4
description
5
6
The SN74CBT3390 is an 8-bit to 16-bit switch
7
used in applications in which two separate data
paths must be multiplexed onto, or demultiplexed
from, a single path. This device can be used for
memory interleaving, in which two different banks
of memory must be addressed simultaneously.
ThisalsocanbeusedtoconnectorisolatethePCI
bus to one or two slots simultaneously.
8
9
10
11
12
13
14
OE1
GND
OE2
Two output enables (OE1 and OE2) control the
data flow. When OE1 is low, A port is connected
to 1B port. When OE2 is low, A port is connected
to 2B port. When both OE1 and OE2 are low, the
A port is connected to both 1B and 2B ports. The
control inputs can be driven with a 5-V CMOS, 5-V
TTL, or an LVTTL driver.
The SN74CBT3390 is characterized for operation
from –40°C to 85°C.
FUNCTION TABLE
INPUTS
FUNCTION
OE1
OE2
L
L
L
A = 1B and A = 2B
A = 1B
H
H
H
L
A = 2B
H
Isolation
Copyright 1998, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3–75
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3390
8-BIT TO 16-BIT FET MULTIPLEXER/DEMULTIPLEXER BUS SWITCH
SCDS071 – JULY 1998
logic diagram (positive logic)
3
1
2
A1
1B1
2B1
25
27
26
A8
1B8
2B8
13
15
OE1
OE2
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
I
CC
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Package thermal impedance, θ (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN
4.5
2
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
V
0.8
85
V
T
A
–40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3–76
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3390
8-BIT TO 16-BIT FET MULTIPLEXER/DEMULTIPLEXER BUS SWITCH
SCDS071 – JULY 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
10
UNIT
V
IK
V
V
V
V
V
= 4.5 V,
= 0
V
CC
CC
CC
CC
CC
I
V = 5.5 V
I
I
I
µA
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 5.5 V or GND
I
±1
I
I
O
= 0,
V = V
I
or GND
3
µA
mA
pF
CC
CC
‡
∆I
CC
Control inputs
Control inputs
One input at 3.4 V,
Other input at V
or GND
2.5
CC
C
C
V = 3 V or 0
I
i
V
= 3 V or 0
= 4.5 V
pF
io(OFF)
O
I = 64 mA
I
V = 0
I
§
V
CC
I = 30 mA
I
Ω
r
on
V = 2.4 V,
I
I = 15 mA
I
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
Measured by the voltage drop between A and B terminals at the indicated current through the switch. On-state resistance is determined by the
lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
¶
t
t
t
A or B
OE
B or A
A or B
A or B
ns
ns
ns
pd
en
OE
dis
¶
The propagation delay is based on the RC time constant of the typical on-state resistance of the switch and a load capacitance of 50 pF, when
driven by an ideal voltage source (zero output impedance).
3–77
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBT3390
8-BIT TO 16-BIT FET MULTIPLEXER/DEMULTIPLEXER BUS SWITCH
SCDS071 – JULY 1998
PARAMETER MEASUREMENT INFORMATION
TEST
S1
7 V
Open
GND
S1
t
Open
7 V
pd
/t
500 Ω
From Output
Under Test
t
PLZ PZL
/t
t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
Output
Control
(low-level
enabling)
3 V
0 V
1.5 V
1.5 V
LOAD CIRCUIT
t
PZL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
V
+ 0.3 V
1.5 V
1.5 V
OL
V
OL
(see Note B)
t
PHZ
t
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
V
OH
– 0.3 V
0 V
1.5 V
Output
1.5 V
1.5 V
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
3–78
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
相关型号：
SN74CBT34X245DBB
CBT/FST/QS/5C/B SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO80, PLASTIC, TSOP-80
TI
©2020 ICPDF网 联系我们和版权申明