SN74CBTD16210DGVR [TI]
具有电平转换器和 2 个控制输入的 5V、1:1 (SPST)、20 通道 FET 总线开关 | DGV | 48 | -40 to 85;
| 型号： | SN74CBTD16210DGVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电平转换器和 2 个控制输入的 5V、1:1 (SPST)、20 通道 FET 总线开关 | DGV | 48 | -40 to 85 开关 驱动 光电二极管 逻辑集成电路 总线驱动器 总线收发器 转换器 电平转换器 |
| 文件： | 总6页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBTD16210
20-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS049C – MARCH 1998 – REVISED MAY 1998
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
Designed to Be Used in Level-Shifting
Applications
NC
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
2A1
2A2
1OE
2OE
1B1
1B2
1
48
47
46
45
2
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
3
4
5
44 1B3
43 1B4
6
7
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1B5
GND
1B6
1B7
1B8
1B9
1B10
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
description
8
9
The SN74CBTD16210 provides 20 bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
delay. A diode to V
is integrated in the circuit to
CC
allow for level shifting between 5-V inputs and
3.3-V outputs.
V
CC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
The device is organized as a dual 10-bit bus
switch with separate output-enable (OE) inputs. It
can be used as two 10-bit bus switches or as one
20-bit bus switch. When OE is low, the associated
10-bit bus switch is on and A port is connected to
B port. When OE is high, the switch is open, and
a high-impedance state exists between the ports.
The SN74CBTD16210 is characterized for
operation from –40°C to 85°C.
NC – No internal connection
FUNCTION TABLE
(each 10-bit bus switch)
INPUT
FUNCTION
OE
L
A port = B port
Z
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTD16210
20-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS049C – MARCH 1998 – REVISED MAY 1998
logic diagram (positive logic)
2
46
36
1A1
1B1
12
1A10
1B10
48
13
1OE
2A1
35
2B1
24
47
25
2A10
2OE
2B10
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN
4.5
2
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
V
0.8
85
V
T
A
–40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTD16210
20-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS049C – MARCH 1998 – REVISED MAY 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
= 4.5 V,
–1.2
V
IK
CC
See Figure 2
I
OH
V
V
V
V
= 0 V,
V = 5.5 V
10
±1
CC
CC
CC
CC
I
I
µA
I
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 5.5 V or GND
I
I
I
O
= 0,
V = V
or GND
1.5
2.5
mA
mA
pF
CC
I
CC
‡
∆I
CC
Control inputs
One input at 3.4 V,
Other inputs at V
or GND
CC
C
C
Control inputs V = 3 V or 0
4.5
5.5
5
i
I
V
O
= 3 V or 0,
OE = V
CC
pF
io(OFF)
I = 64 mA
I
7
7
V = 0
I
§
I = 30 mA
I
5
V
CC
= 4.5 V
Ω
r
on
V = 2.4 V,
I
I = 15 mA
I
35
50
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
¶
t
t
t
A or B
OE
B or A
A or B
A or B
0.25
9.8
ns
ns
ns
pd
1.5
1.5
en
OE
8.9
dis
¶
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTD16210
20-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS049C – MARCH 1998 – REVISED MAY 1998
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
S1
S1
500 Ω
t
pd
Open
7 V
From Output
Under Test
t
/t
GND
PLZ PZL
t
/t
Open
C
= 50 pF
PHZ PZH
L
500 Ω
(see Note A)
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PZL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
V
OL
+ 0.3 V
1.5 V
1.5 V
(see Note B)
V
OL
t
PHZ
t
t
PHL
PZH
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
V
OH
– 0.3 V
0 V
1.5 V
Output
1.5 V
1.5 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTD16210
20-BIT FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS049C – MARCH 1998 – REVISED MAY 1998
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE HIGH
OUTPUT VOLTAGE HIGH
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
4
3.75
3.5
4
3.75
3.5
–100 µA
T
A
= 85°C
T = 25°C
A
–100 µA
–6 mA
–12 mA
–24 mA
–6 mA
–12 mA
–24 mA
3.25
3.25
3
3
2.75
2.75
2.5
2.5
2.25
2.25
2
1.75
1.5
2
1.75
1.5
4.5
4.75
4.5
4.75
5.5
5.75
5.5
5.75
5
5.25
5
5.25
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4
3.75
3.5
T
A
= 0°C
–100 µA
–6 mA
–12 mA
–24 mA
3.25
3
2.75
2.5
2.25
2
1.75
1.5
4.5
4.75
5.5
5.75
5
5.25
V
CC
– Supply Voltage – V
Figure 2. V
Values
OH
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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