SN74CBTD3306PWRG3 [TI]
DUAL FET BUS SWITCH WITH LEVEL SHIFTING; 与电平转换双FET总线开关
| 型号： | SN74CBTD3306PWRG3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL FET BUS SWITCH WITH LEVEL SHIFTING |
| 文件： | 总12页 (文件大小：755K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74CBTD3306
DUAL FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS030L − JANUARY 1996 − REVISED JANUARY 2004
D OR PW PACKAGE
(TOP VIEW)
D
D
D
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
Designed to Be Used in Level-Shifting
Applications
1OE
1A
VCC
2OE
2B
1
2
3
4
8
7
6
5
1B
description/ordering information
2A
GND
The SN74CBTD3306 features two independent
line switches. Each switch is disabled when the
associated output-enable (OE) input is high. A
diode to V is integrated on the chip to allow for
CC
level shifting from 5-V signals at the device inputs
to 3.3-V signals at the device outputs.
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
T
PACKAGE
A
PART NUMBER
SN74CBTD3306D
SN74CBTD3306DR
SN74CBTD3306PW
SN74CBTD3306PWR
Tube
SOIC − D
CC306
CC306
Tape and reel
Tube
−40°C to 85°C
TSSOP − PW
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each bus switch)
INPUT
FUNCTION
OE
L
A port = B port
Disconnect
H
logic diagram (positive logic)
2
1
3
6
1B
2B
1A
1OE
5
7
2A
2OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTD3306
DUAL FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS030L − JANUARY 1996 − REVISED JANUARY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
I/O
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
JA
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
4.5
2
MAX
UNIT
V
V
V
V
T
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
V
0.8
85
V
−40
°C
A
In applications with fast edge rates, multiple outputs switching, and operating at high frequencies, the output may have little or no level-shifting
effect.
NOTE 3: All unused control inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
= 4.5 V,
I = −18 mA
I
−1.2
V
IK
CC
See Figure 2
OH
I
V
V
V
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 5.5 V or GND
1
1.5
2.5
μA
mA
mA
pF
I
CC
CC
CC
I
I
I
O
= 0,
V = V or GND
I CC
CC
§
ΔI
Control inputs
Control inputs
One input at 3.4 V,
Other inputs at V or GND
CC
CC
C
C
V = 3 V or 0
I
3
i
V
O
= 3 V or 0,
OE = V
CC
4
5
pF
io(OFF)
I = 64 mA
I
7
7
V = 0
I
¶
V
CC
= 4.5 V
I = 30 mA
I
5
Ω
r
on
V = 2.4 V,
I
I = 15 mA
I
35
50
‡
§
¶
All typical values are at V = 5 V, T = 25°C.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V or GND.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
CC
A
CC
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTD3306
DUAL FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS030L − JANUARY 1996 − REVISED JANUARY 2004
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
†
t
t
t
A or B
OE
B or A
A or B
A or B
0.25
5.4
ns
ns
ns
pd
en
dis
2.1
1
4.7
OE
†
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
7 V
TEST
S1
Open
7 V
S1
Open
500 Ω
t
pd
From Output
Under Test
t
t
/t
PLZ PZL
GND
/t
Open
PHZ PZH
C = 50 pF
(see Note A)
L
500 Ω
3 V
0 V
Output
Control
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
1.5 V
1.5 V
1.5 V
Input
V
V
+ 0.3 V
OL
(see Note B)
V
OL
OH
0 V
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
V
OH
− 0.3 V
OH
1.5 V
1.5 V
1.5 V
Output
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PHL
PHZ
dis
are the same as t
PZH
en
are the same as t .
PLH pd
Figure 1. Load Circuit and Voltage Waveforms
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTD3306
DUAL FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS030L − JANUARY 1996 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE HIGH
vs
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
4
3.75
3.5
4
3.75
3.5
T
A
= 85°C
T = 25°C
A
100 μA
100 μA
6 mA
12 mA
6 mA
12 mA
24 mA
3.25
3.25
24 mA
3
3
2.75
2.75
2.5
2.25
2
2.5
2.25
2
1.75
1.5
1.75
1.5
4.5
4.75
5
5.25
5.5
5.75
4.5
4.75
5
5.25
5.5
5.75
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4
3.75
3.5
T
A
= 0°C
100 μA
3.25
6 mA
12 mA
3
24 mA
2.75
2.5
2.25
2
1.75
1.5
4.5
4.75
5
5.25
5.5
5.75
V
CC
− Supply Voltage − V
Figure 2. V Values
OH
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
SN74CBTD3306D
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CC306
SN74CBTD3306DE4
SN74CBTD3306DG4
SN74CBTD3306DR
SN74CBTD3306DRE4
SN74CBTD3306DRG4
SN74CBTD3306PW
SN74CBTD3306PWE4
SN74CBTD3306PWG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
75
75
Green (RoHS
& no Sb/Br)
CC306
CC306
CC306
CC306
CC306
CC306
CC306
CC306
SOIC
Green (RoHS
& no Sb/Br)
SOIC
D
2500
2500
2500
150
150
150
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
PW
PW
PW
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74CBTD3306PWLE
SN74CBTD3306PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
8
8
TBD
Call TI
-40 to 85
-40 to 85
2000
2000
Green (RoHS CU NIPDAU | CU SN
& no Sb/Br)
Level-1-260C-UNLIM
CC306
CC306
SN74CBTD3306PWRE4
ACTIVE
TSSOP
PW
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
SN74CBTD3306PWRG3
SN74CBTD3306PWRG4
PREVIEW
ACTIVE
TSSOP
TSSOP
PW
PW
8
8
2000
2000
TBD
Call TI
Call TI
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CC306
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74CBTD3306DR
SN74CBTD3306DR
SN74CBTD3306PWR
SN74CBTD3306PWR
SOIC
SOIC
D
D
8
8
8
8
2500
2500
2000
2000
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
6.4
6.4
7.0
7.0
5.2
5.2
3.6
3.6
2.1
2.1
1.6
1.6
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
TSSOP
TSSOP
PW
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74CBTD3306DR
SN74CBTD3306DR
SN74CBTD3306PWR
SN74CBTD3306PWR
SOIC
SOIC
D
D
8
8
8
8
2500
2500
2000
2000
340.5
367.0
364.0
367.0
338.1
367.0
364.0
367.0
20.6
35.0
27.0
35.0
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
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