SN74CBTK32245GKER [TI]
32 BIT FET BUS SWITCH WITH ACTIVE CLAMP UNDERSHOOT PROTECTION CIRCUIT; 有源钳位冲保护电路32位FET总线开关
| 型号： | SN74CBTK32245GKER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 32 BIT FET BUS SWITCH WITH ACTIVE CLAMP UNDERSHOOT PROTECTION CIRCUIT |
| 文件： | 总10页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢈ ꢉ ꢋꢅꢌ ꢆ ꢍ ꢎꢆ ꢅꢏꢀ ꢀ ꢐꢌ ꢆꢄ ꢑ
ꢐ ꢌ ꢆꢑ ꢒꢄꢆ ꢌ ꢓꢎꢋꢄꢔ ꢒꢕ ꢖ ꢏꢁꢗ ꢎꢘꢀꢑ ꢙꢙ ꢆꢋꢖꢘ ꢙꢆ ꢎꢄ ꢆꢌ ꢙ ꢁ ꢄ ꢌꢘ ꢄꢏ ꢌ ꢆ
SCDS106E − APRIL 2000 − REVISED SEPTEMBER 2003
D
D
D
D
Member of the Texas Instruments
Widebus+ Family
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
D
D
D
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
I
Supports Partial-Power-Down Mode
off
Operation
D
Active-Clamp Undershoot-Protection
Circuit on the I/Os Clamps Undershoots Up
To −2 V
− 1000-V Charged-Device Model (C101)
description/ordering information
The SN74CBTK32245 provides 32 bits of high-speed TTL-compatible bus switching. The low on-state
resistance of the switch allows connections to be made with minimal propagation delay.
The A and B ports have an active-clamp undershoot-protection circuit. When there is an undershoot, the
active-clamp circuit is enabled and current from V
transistor from turning on.
is supplied to clamp the output, preventing the pass
CC
The device is organized as four 8-bit bus switches, two 16-bit bus switches, or one 32-bit bus switch. When the
output-enable (OE) input is low, the switch is on and port A is connected to port B. When OE is high, the switch
is open and the high-impedance state exists between the two ports.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
LFBGA − GKE
LFBGA − ZKE (Pb-free)
SN74CBTK32245GKER
SN74CBTK32245ZKER
−40°C to 85°C
Tape and reel
KT245
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit bus switch)
INPUT
FUNCTION
OE
L
A port = B port
Disconnect
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
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SCDS106E − APRIL 2000 − REVISED SEPTEMBER 2003
GKE OR ZKE PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1B2
1B4
1B6
1B8
2B2
2B4
2B6
2B7
3B2
3B4
3B6
3B8
4B2
4B4
4B6
4B7
1B1
1B3
1B5
1B7
2B1
2B3
2B5
2B8
3B1
3B3
3B5
3B7
4B1
4B3
4B5
4B8
NC
GND
1OE
GND
1A1
1A3
1A5
1A7
2A1
2A3
2A5
2A8
3A1
3A3
3A5
3A7
4A1
4A3
4A5
4A8
1A2
1A4
1A6
1A8
2A2
2A4
2A6
2A7
3A2
3A4
3A6
3A8
4A2
4A4
4A6
4A7
A
B
C
D
E
F
V
CC
V
CC
GND
GND
GND
GND
V
CC
V
CC
G
H
J
GND
NC
GND
2OE
3OE
GND
G
H
J
NC
K
L
GND
K
L
V
CC
V
CC
M
N
P
R
T
GND
GND
GND
GND
M
N
P
R
T
V
CC
V
CC
GND
NC
GND
4OE
NC − No internal connection
2
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SCDS106E − APRIL 2000 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
V
CC
V
CC
V
CC
V
CC
†
†
†
†
UC
UC
UC
UC
A5
A2
D1
E5
E2
H2
1A1
1B1
1B8
2A1
2B1
2B8
V
V
V
V
CC
CC
CC
CC
†
†
†
†
UC
UC
UC
UC
D6
A4
H5
H4
2A8
2OE
1A8
1OE
V
CC
V
CC
V
CC
V
CC
†
†
†
†
UC
UC
UC
UC
J5
J2
N5
N2
T2
3A1
3A8
3B1
3B8
4A1
4B1
4B8
V
V
V
V
CC
CC
CC
CC
†
†
†
†
UC
UC
UC
UC
M6
J4
M1
T5
T4
4A8
4OE
3OE
†
Undershoot clamp
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK I/O
Package thermal impedance, θ (see Note 2): GKE/ZKE package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3
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ꢐꢌ ꢆ ꢑ ꢒ ꢄ ꢆꢌ ꢓ ꢎꢋꢄ ꢔꢒ ꢕꢖ ꢏꢁ ꢗꢎ ꢘꢀ ꢑꢙ ꢙꢆꢋꢖ ꢘꢙ ꢆ ꢎꢄꢆ ꢌꢙ ꢁ ꢄꢌ ꢘꢄꢏꢌ ꢆ
SCDS106E − APRIL 2000 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
MIN
4
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
2
V
0.8
85
V
T
A
−40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to TI application report
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = −18 mA
MIN TYP
MAX
−1.2
−2
UNIT
V
V
V
V
V
V
V
V
V
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 0,
IK
CC
CC
CC
CC
CC
CC
I
0 mA ≥ I ≥ −50 mA,
OE = 5.5 V
V
IKU
I
I
I
I
V = 5.5 V or GND
I
5
µA
µA
µA
mA
pF
pF
I
V or V = 0 to 5.5 V
20
off
I
O
= 5.5 V,
= 5.5 V,
V = V
or GND,
I = 0
O
6
CC
I
CC
‡
∆I
CC
Control inputs
One input at 3.4 V,
Other inputs at V
CC
or GND
3.5
C
C
Control inputs V = 3 V or 0
3.5
5.5
i
I
V
O
= 3 V or 0,
OE = V
CC
io(OFF)
V
= 4 V,
CC
V
I
= 2.4 V,
I = 15 mA
I
14
20
TYP at V
= 4 V
CC
§
I = 64 mA
I
5
5
8
7
7
Ω
r
on
V = 0
I
V
CC
= 4.5 V
I = 30 mA
I
V = 2.4 V,
I
I = 15 mA
I
12
†
‡
§
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL-voltage level, rather than V
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
or GND.
CC
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
V
= 5 V
CC
0.5 V
V
= 4 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
¶
t
A or B
OE
B or A
A or B
A or B
0.35
7.4
0.25
4.9
ns
ns
ns
pd
t
t
1.6
4.2
en
7.4
7.5
OE
dis
¶
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
4
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ꢐ ꢌ ꢆꢑ ꢒꢄꢆ ꢌ ꢓꢎꢋꢄꢔ ꢒꢕ ꢖ ꢏꢁꢗ ꢎꢘꢀꢑ ꢙꢙ ꢆꢋꢖꢘ ꢙꢆ ꢎꢄ ꢆꢌ ꢙ ꢁ ꢄ ꢌꢘ ꢄꢏ ꢌ ꢆ
SCDS106E − APRIL 2000 − REVISED SEPTEMBER 2003
undershoot characteristics
†
PARAMETER
TEST CONDITIONS
See Figures 1 and 2, and Table 1
= 5 V (unless otherwise noted), T = 25°C.
MIN
TYP
MAX
UNIT
V
2
V
−0.3
V
OUTU
OH
†
All typical values are at V
CC
A
V
CC
V
TR
R1
50 Ω
DUT
R2
10 pF
5.5 V
−2 V
V
IN
0 V
Figure 1. Device Test Setup
Figure 2. Transient Input Voltage Waveform
Table 1. Device Test Conditions
PARAMETER
VALUE
UNIT
‡
B port under test
See Figure 1
V
See Figure 2
V
ns
ns
ns
kΩ
V
IN
t
w
20
2
t
r
t
2
f
R1 = R2
100
11
5.5
V
V
TR
V
CC
‡
Other B-port outputs are open
5
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SCDS106E − APRIL 2000 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
7 V
TEST
S1
S1
Open
GND
500 Ω
t
Open
7 V
From Output
Under Test
pd
/t
t
PLZ PZL
t
/t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
3 V
0 V
Output
Control
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
(see Note B)
OL
OH
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
V
OH
− 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74CBTK32245GKER
SN74CBTK32245ZKER
ACTIVE
ACTIVE
LFBGA
LFBGA
GKE
96
96
1000
TBD
SNPB
Level-3-220C-168 HR
Level-3-250C-168 HR
ZKE
1000 Green (RoHS &
no Sb/Br)
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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