SN74CBTLV16235DGGR [TI]

CBTLV/3B SERIES, 18 1 LINE TO 2 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64;


型号：	SN74CBTLV16235DGGR
厂家：	TEXAS INSTRUMENTS
描述：	CBTLV/3B SERIES, 18 1 LINE TO 2 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64 解复用器
文件：	总8页 (文件大小：140K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ ꢋꢌ ꢍ

ꢇꢎ ꢏꢐꢈ ꢎꢇꢆꢑꢒ ꢓ ꢉ ꢔ ꢐꢅꢕ ꢆ ꢉ ꢐꢎ ꢖꢐ ꢋ ꢖ ꢓꢆ ꢗ ꢘꢇꢆ ꢕꢙ ꢇꢓ ꢚꢓꢛꢜ ꢝꢓꢗ ꢘꢇꢆꢕ ꢙ ꢇꢓ ꢚꢓ ꢛ

SCDS060F − MARCH 1998 − REVISED OCTOBER 2003

DGG PACKAGE

(TOP VIEW)

4-Ω Switch Connection Between Two Ports

Rail-to-Rail Switching on Data I/O Ports

Supports Partial-Power-Down Mode

2B1

2B2

1B1

1B2

3B1

3B2

off

Operation

Break-Before-Make Feature

description/ordering information

4B1

4B2

6B1

6B2

8B1

8B2

GND

The SN74CBTLV16235 is an 18-bit 1-of-2 FET

multiplexer/demultiplexer used in applications in

which two separate data paths must be

multiplexed onto, or demultiplexed from, a single

path. This device can be used for memory

interleaving, where two different banks of memory

need to be addressed simultaneously.

5B1

5B2

7B1

7B2

GND

VCC

9B1

9B2

10A

11B1

11B2

12A

13B1

13B2

14A

15B1

15B2

16A

17B1

17B2

18A

GND

The device is organized as a dual 9-bit 1-of-2

multiplexer/demultiplexer with separate control

inputs. It can be used as two 9-bit

multiplexers/demultiplexers or as one 18-bit

multiplexer/demultiplexer. Two select (S0 and S1)

inputs control the data flow. When the test (T0 and

T1) inputs are asserted, port A is connected to

both ports B1 and B2. The control inputs can be

driven with a low-voltage TTL or an SSTL_3

driver.

10B1

10B2

11A

12B1

12B2

13A

14B1

14B2

15A

16B1

16B2

17A

The SN74CBTLV16235 is specified by the

break-before-make design to have no through

current when switching directions.

This

device

fully

specified

for

18B1

18B2

GND

partial-power-down applications using I . The I

off

feature ensures that damaging current will not

backflow through the device when it is powered

down. The device has isolation during power off.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

−40°C to 85°C TSSOP − DGG Tape and reel

SN74CBTLV16235GR

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈꢉ ꢊ ꢋꢌ ꢍ

ꢇ ꢎꢏꢐꢈ ꢎꢇꢆꢑ ꢒꢓ ꢉ ꢔ ꢐꢅꢕ ꢆ ꢉ ꢐꢎ ꢖꢐꢋ ꢖꢓ ꢆ ꢗꢘ ꢇꢆ ꢕꢙ ꢇꢓ ꢚꢓꢛꢜ ꢝꢓꢗ ꢘꢇꢆ ꢕꢙ ꢇꢓ ꢚꢓꢛ

SCDS060F − MARCH 1998 − REVISED OCTOBER 2003

FUNCTION TABLE

(each 9-bit multiplexer/demultiplexer)

INPUTS

FUNCTION

A port = B1 port

A port = B2 port

A port = B1 port = B2 port

logic diagram (positive logic)

1B1

1B2

9B1

9B2

10A

10B1

10B2

18A

18B1

18B2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ ꢋꢌ ꢍ

ꢇꢎ ꢏꢐꢈ ꢎꢇꢆꢑꢒ ꢓ ꢉ ꢔ ꢐꢅꢕ ꢆ ꢉ ꢐꢎ ꢖꢐ ꢋ ꢖ ꢓꢆ ꢗ ꢘꢇꢆ ꢕꢙ ꢇꢓ ꢚꢓꢛꢜ ꢝꢓꢗ ꢘꢇꢆꢕ ꢙ ꢇꢓ ꢚꢓ ꢛ

SCDS060F − MARCH 1998 − REVISED OCTOBER 2003

simplified schematic, each FET switch

(OE)

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W

stg

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

MIN

2.3

1.7

MAX

UNIT

Supply voltage

3.6

= 2.3 V to 2.7 V

= 2.7 V to 3.6 V

= 2.3 V to 2.7 V

= 2.7 V to 3.6 V

High-level control input voltage

0.7

0.8

Low-level control input voltage

Operating free-air temperature

−40

°C

NOTE 3: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to TI application report

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈꢉ ꢊ ꢋꢌ ꢍ

ꢇ ꢎꢏꢐꢈ ꢎꢇꢆꢑ ꢒꢓ ꢉ ꢔ ꢐꢅꢕ ꢆ ꢉ ꢐꢎ ꢖꢐꢋ ꢖꢓ ꢆ ꢗꢘ ꢇꢆ ꢕꢙ ꢇꢓ ꢚꢓꢛꢜ ꢝꢓꢗ ꢘꢇꢆ ꢕꢙ ꢇꢓ ꢚꢓꢛ

SCDS060F − MARCH 1998 − REVISED OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

PARAMETER

TEST CONDITIONS

I = −18 mA

MIN TYP

MAX

−1.2

UNIT

= 3 V,

= 3.6 V,

= 0,

V = V

I CC

or GND

µA

V or V = 0 to 3.6 V

off

= 3.6 V,

= 0,

V = V

I CC

or GND

‡

∆I

Control input

One input at 3 V,

Other inputs at V

or GND

300

Control input

A port

V = 3 V or 0

= 3 V or 0

io(OFF)

B port

I = 64 mA

V = 0

= 2.3 V,

I = 24 mA

TYP at V

= 2.5 V

V = 1.7 V,

I = 15 mA

Ω

I = 64 mA

V = 0

= 3 V

I = 24 mA

V = 2.4 V,

I = 15 mA

†

‡

All typical values are at V

= 3.3 V (unless otherwise noted), T = 25°C.

This is the increase in supply current for each input that is at the specified voltage level, rather than V

or GND.

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by

the lower of the voltages of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 1)

= 2.5 V

= 3.3 V

0.2 V

0.3 V

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN MAX

A or B

B or A

A or B

dis

A or B

dis

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when

driven by an ideal voltage source (zero output impedance).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ ꢋꢌ ꢍ

ꢇꢎ ꢏꢐꢈ ꢎꢇꢆꢑꢒ ꢓ ꢉ ꢔ ꢐꢅꢕ ꢆ ꢉ ꢐꢎ ꢖꢐ ꢋ ꢖ ꢓꢆ ꢗ ꢘꢇꢆ ꢕꢙ ꢇꢓ ꢚꢓꢛꢜ ꢝꢓꢗ ꢘꢇꢆꢕ ꢙ ꢇꢓ ꢚꢓ ꢛ

SCDS060F − MARCH 1998 − REVISED OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION

2 × V

TEST

Open

PLH PHL

From Output

Under Test

2 × V

GND

PLZ PZL

GND

PHZ PZH

(see Note A)

∆

2.5 V 0.2 V

3.3 V 0.3 V

500 Ω

0.15 V

0.3 V

30 pF

50 pF

LOAD CIRCUIT

Timing Input

0 V

Input

Data Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

Control

Input

0 V

PZL

PLZ

+ V

PHL

PLH

Output

Waveform 1

Output

S1 at 2 × V

(see Note B)

∆

PHL

PLH

PZH

PHZ

− V

Output

Waveform 2

S1 at GND

∆

Output

≈0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A.

C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.

D. The outputs are measured one at a time with one transition per measurement.

and t

are the same as t

PLZ

PZL

PLH

PHZ

PZH

PHL

dis

are the same as t

are the same as t .

H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

11-Oct-2007

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SN74CBTLV16235GR

PREVIEW

TSSOP

DGG

2000

TBD

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27

0,17

0,08

0,50

6,20

6,00

8,30

7,90

0,15 NOM

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

DIM

A MAX

12,60

12,40

14,10

13,90

17,10

16,90

A MIN

4040078/F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SN74CBTLV16235DGGR [TI]

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