SN74CBTLV3125_07 [TI]
LOW-VOLTAGE QUADRUPLE FET BUS SWITCH; 低压翻两番FET总线开关
| 型号： | SN74CBTLV3125_07 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-VOLTAGE QUADRUPLE FET BUS SWITCH |
| 文件： | 总18页 (文件大小：824K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ ꢋꢌ
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SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003
D
D
D
Standard ’125-Type Pinout
D
D
I
Supports Partial-Power-Down Mode
off
Operation
5-Ω Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D, DGV, NS, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
DBQ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
4OE
4A
4B
3OE
3A
3B
NC
1OE
1A
1B
2OE
2A
1OE
1A
1B
2OE
2A
2B
V
CC
4OE
CC
1
14
4A
4B
3OE
3A
3B
1A
1B
13 4OE
12 4A
2
3
4
5
6
11
10
9
2OE
2A
4B
3OE
3A
8
2B
GND
GND
2B
NC
7
8
NC − No internal connection
description/ordering information
The SN74CBTLV3125 quadruple FET bus switch features independent line switches. Each switch is disabled
when the associated output-enable (OE) input is high.
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
SOIC − D
Tape and reel
SN74CBTLV3125RGYR
SN74CBTLV3125D
CL125
Tube
CBTLV3125
Tape and reel
Tape and reel
SN74CBTLV3125DR
SN74CBTLV3125NSR
SN74CBTLV3125DBQR
SN74CBTLV3125PWR
SN74CBTLV3125DGVR
−40°C to 85°C SOP − NS
CBTLV3125
CL125
SSOP (QSOP) − DBQ Tape and reel
TSSOP − PW
TVSOP − DGV
Tape and reel
Tape and reel
CL125
CL125
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈꢉ ꢊ ꢋꢌ
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SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003
FUNCTION TABLE
(each bus switch)
INPUT
OE
FUNCTION
L
A port = B port
Disconnect
H
logic diagram (positive logic)
2
1
3
6
1A
1B
2B
3B
4B
SW
SW
SW
SW
1OE
5
4
2A
2OE
9
8
3A
10
3OE
12
13
11
4A
4OE
Pin numbers shown are for the D, DGV, NS, PW, and RGY packages.
simplified schematic, each FET switch
A
B
(OE)
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ ꢋꢌ
ꢇ ꢍ ꢎꢏꢈꢍ ꢇꢆꢐꢑ ꢒ ꢓ ꢔꢐꢕꢖ ꢔꢗꢇ ꢒ ꢘ ꢒꢆ ꢅꢔꢀ ꢀ ꢎꢙ ꢆꢄ ꢚ
SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK I/O
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
(see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
(see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
MIN
2.3
1.7
2
MAX
UNIT
V
V
Supply voltage
3.6
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
High-level control input voltage
V
IH
0.7
0.8
85
V
IL
Low-level control input voltage
Operating free-air temperature
V
T
A
−40
°C
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈꢉ ꢊ ꢋꢌ
ꢇ ꢍꢎꢏꢈ ꢍꢇꢆꢐ ꢑꢒ ꢓ ꢔꢐꢕ ꢖꢔꢗ ꢇ ꢒ ꢘꢒ ꢆ ꢅꢔ ꢀ ꢀꢎ ꢙ ꢆꢄ ꢚ
SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = −18 mA
MIN TYP
MAX
−1.2
1
UNIT
V
V
V
V
V
V
V
= 3 V,
IK
CC
CC
CC
CC
CC
I
I
I
I
= 3.6 V,
= 0,
V = V
I CC
or GND
µA
µA
µA
µA
pF
I
V or V = 0 to 3.6 V
10
off
I
O
= 3.6 V,
= 3.6 V,
I
O
= 0,
V = V
I CC
or GND
10
CC
‡
∆I
CC
Control inputs
One input at 3 V,
Other inputs at V
CC
or GND
300
C
C
Control inputs V = 3 V or 0
2.5
7
i
I
V
O
= 3 V or 0,
OE = V
CC
pF
io(OFF)
I = 64 mA
5
8
8
I
V = 0
I
V
= 2.3 V,
CC
I = 24 mA
I
5
TYP at V
CC
= 2.5 V
V = 1.7 V,
I
I = 15 mA
I
27
5
40
7
§
on
Ω
r
I = 64 mA
I
V = 0
I
V
CC
= 3 V
I = 24 mA
I
5
7
V = 2.4 V,
I
I = 15 mA
I
10
15
†
‡
§
All typical values are at V
This is the increase in supply current for each input that is at the specified voltage level, rather than V
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
= 3.3 V (unless otherwise noted), T = 25°C.
A
CC
or GND.
CC
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 2.5 V
0.2 V
V
= 3.3 V
CC
CC
0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
0.15
4.6
MIN
MAX
¶
t
t
t
A or B
OE
B or A
A or B
A or B
0.25
4.4
ns
ns
ns
pd
en
2
2
1
1.1
3.9
4.2
OE
dis
¶
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ ꢋꢌ
ꢇ ꢍ ꢎꢏꢈꢍ ꢇꢆꢐꢑ ꢒ ꢓ ꢔꢐꢕꢖ ꢔꢗꢇ ꢒ ꢘ ꢒꢆ ꢅꢔꢀ ꢀ ꢎꢙ ꢆꢄ ꢚ
SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
t
/t
Open
Open
R
PLH PHL
L
From Output
Under Test
t
/t
2 × V
CC
GND
PLZ PZL
GND
t
/t
PHZ PZH
C
L
R
L
(see Note A)
C
V
∆
R
V
CC
L
L
2.5 V 0.2 V
3.3 V 0.3 V
500 Ω
500 Ω
0.15 V
0.3 V
30 pF
50 pF
LOAD CIRCUIT
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
/2
Input
CC
0 V
V
0 V
t
t
t
PHL
t
t
PLH
PZL
PLZ
+ V
Output
Waveform 1
V
V
OH
CC
V
V
/2
/2
V
CC
/2
V
CC
/2
/2
Output
CC
S1 at 2 × V
(see Note B)
CC
V
OL
∆
V
OL
OL
t
t
t
PHL
PLH
/2
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
74CBTLV3125DBQRE4
74CBTLV3125DBQRG4
74CBTLV3125DGVRE4
74CBTLV3125DGVRG4
74CBTLV3125NSRG4
74CBTLV3125PWRE4
74CBTLV3125PWRG4
74CBTLV3125RGYRG4
SN74CBTLV3125D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
16
16
14
14
14
14
14
14
14
16
14
14
14
14
14
14
14
14
14
14
14
14
14
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
DBQ
DGV
DGV
NS
PW
PW
RGY
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TVSOP
TVSOP
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBTLV3125DBQR
SN74CBTLV3125DE4
SN74CBTLV3125DG4
SN74CBTLV3125DGVR
SN74CBTLV3125DR
SSOP/
QSOP
DBQ
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
SOIC
TVSOP
SOIC
SOIC
SOIC
SO
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBTLV3125DRE4
SN74CBTLV3125DRG4
SN74CBTLV3125NSR
SN74CBTLV3125NSRE4
SN74CBTLV3125PW
SN74CBTLV3125PWE4
SN74CBTLV3125PWG4
SN74CBTLV3125PWR
SN74CBTLV3125RGYR
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NS
NS
PW
PW
PW
PW
RGY
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
QFN
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
180
(mm)
0
SN74CBTLV3125DBQR
SN74CBTLV3125DGVR
SN74CBTLV3125DR
DBQ
DGV
D
16
14
14
14
14
14
SITE 27
SITE 41
SITE 41
SITE 41
SITE 41
SITE 41
6.4
6.8
6.5
8.2
7.0
3.85
5.2
4.0
2.1
1.6
2.1
2.5
1.6
1.35
8
8
12
16
16
16
12
12
Q1
Q1
Q1
Q1
Q1
Q1
12
16
16
12
12
9.0
8
SN74CBTLV3125NSR
SN74CBTLV3125PWR
SN74CBTLV3125RGYR
NS
10.5
5.6
12
8
PW
RGY
3.85
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74CBTLV3125DBQR
SN74CBTLV3125DGVR
SN74CBTLV3125DR
DBQ
DGV
D
16
14
14
14
14
14
SITE 27
SITE 41
SITE 41
SITE 41
SITE 41
SITE 41
342.9
346.0
346.0
346.0
346.0
190.0
336.6
346.0
346.0
346.0
346.0
212.7
20.64
29.0
33.0
33.0
29.0
31.75
SN74CBTLV3125NSR
SN74CBTLV3125PWR
SN74CBTLV3125RGYR
NS
PW
RGY
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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