SN74F112NE4 [TI]
具有清零和预置端的双路负边沿触发式 J-K 触发器 | N | 16 | 0 to 70;
| 型号： | SN74F112NE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有清零和预置端的双路负边沿触发式 J-K 触发器 | N | 16 | 0 to 70 光电二极管 逻辑集成电路 触发器 锁存器 |
| 文件： | 总5页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74F112
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993
D OR N PACKAGE
(TOP VIEW)
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
V
1CLK
1K
1
2
3
4
5
6
7
8
16
CC
description
15 1CLR
14 2CLR
1J
The SN74F112 contains two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), dataattheJandKinputsmeetingthesetup
time requirements is transferred to the outputs on
the negative-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold-time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. The SN74F112 can perform
as a toggle flip-flop by tying J and K high.
13
12
11
10
9
2CLK
2K
1PRE
1Q
2J
1Q
2PRE
2Q
2Q
GND
The SN74F112 is characterized for operation from
0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
H
CLK
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
†
H
†
L
L
X
H
H
H
↓
Q
Q
0
0
H
H
↓
H
L
L
H
L
H
H
↓
H
H
X
L
H
H
H
↓
H
X
Toggle
H
H
H
Q
Q
0
0
†
The output levels in this configuration are not guaranteed to
meet the minimum levels for V . Furthermore, this
OH
configuration is nonstable; that is, it will not persist when
either PRE or CLR returns to its inactive (high) level.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F112
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993
†
logic symbol
4
S
1PRE
1J
5
6
3
1Q
1Q
1J
1
1CLK
1K
C1
2
1K
R
15
1CLR
10
11
13
12
14
2PRE
2J
9
7
2Q
2Q
2CLK
2K
2CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram, each flip-flop (positive logic)
Q
Q
PRE
CLR
K
J
CLK
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F112
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
V
0.8
–18
– 1
20
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
T
A
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 4.75 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
–1.2
V
IK
I
I
I
I
= – 1 mA
= – 1 mA
= 20 mA
2.5
2.7
3.4
0.3
OH
OH
OL
V
OH
OL
0.5
0.1
V
I
I
V = 7 V
I
mA
µA
I
IH
V = 2.7 V
I
20
J or K
– 0.6
– 3
I
IL
PRE or CLR
CLK
V
= 5.5 V,
V = 0.5 V
mA
CC
I
– 2.4
–150
19
‡
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 0
O
–60
mA
mA
OS
CC
CC
See Note 2
12
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2:
I
is measured with all outputs open, the Q and Q outputs alternately high and the clock input grounded at the time of measurement.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
Clock frequency
Pulse duration
110
0
5
100
MHz
ns
clock
CLK high or low
CLR or PRE low
High
4.5
4.5
4
w
5
5
t
su
Setup time, data before CLK↓
ns
Low
3
3.5
0
High
0
t
t
Hold time, data after CLK↓
ns
ns
h
Low
0
0
§
Setup time, inactive state, data before CLK↓
CLR or PRE high
4
5
su
§
Inactive-state state setup time is also referred to as recovery time.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F112
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993
switching characteristics (see Note 3)
V
C
R
= 5 V,
= 50 pF,
= 500 Ω,
= 25°C
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
CC
L
L
FROM
(INPUT)
TO
(OUTPUT)
= 500Ω,
PARAMETER
UNIT
†
T
A
T
A
= MIN to MAX
MIN
110
1.2
1.2
1.2
1.2
TYP
130
4.6
4.6
4.1
4.1
MAX
MIN
100
1.2
1.2
1.2
1.2
MAX
f
MHz
ns
max
PLH
PHL
PLH
PHL
t
t
t
t
6.5
6.5
6.5
6.5
7.5
7.5
7.5
7.5
CLK
Q or Q
Q or Q
PRE or CLR
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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