SN74F161ADRG4 [TI]
SYNCHRONOUS 4-BIT BINARY COUNTER; 同步4位二进制计数器
| 型号： | SN74F161ADRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS 4-BIT BINARY COUNTER |
| 文件： | 总17页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
D, DB, OR N PACKAGE
(TOP VIEW)
Internal Look-Ahead Circuitry for Fast
Counting
Carry Output for N-Bit Cascading
V
RCO
Q
CLR
CLK
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
Fully Synchronous Operation for Counting
A
description
Q
B
Q
B
C
D
This synchronous, presettable, 4-bit binary
counter has internal carry look-ahead circuitry
for use in high-speed counting designs.
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincident with each other when
C
Q
D
ENT
ENP
GND
LOAD
so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the
output counting spikes that are normally associated with asynchronous (ripple-clock) counters. However,
counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four
flip-flops on the rising (positive-going) edge of CLK.
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because
presettingissynchronous, alowlogiclevelattheload(LOAD)inputdisablesthecounterandcausestheoutputs
to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.
The clear function is asynchronous, and a low logic level at the clear (CLR) input sets all four of the flip-flop
outputs to low, regardless of the levels of CLK, LOAD, ENP, and ENT.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without
additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and
ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a
high-logic-levelpulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used
to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
The SN74F161A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD that modify the
operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter
(whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold
times.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
SOIC – D
SSOP – DB
Tube
SN74F161AN
SN74F161AD
SN74F161ADR
SN74F161ADBR
SN74F161AN
Tube
0°C to 70°C
F161A
Tape and reel
Tape and reel
F161A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
state diagram
0
1
2
3
4
5
15
14
13
12
6
7
8
11
10
9
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
logic diagram (positive logic)
1
CLR
9
LOAD
10
ENT
15
7
RCO
ENP
R
14
Q
A
G2
2
CLK
1, 2T/C3
3
A
1, 3D
M1
R
13
Q
G2
B
1, 2T/C3
4
B
1, 3D
M1
R
12
Q
G2
C
1, 2T/C3
5
C
1, 3D
M1
R
11
Q
G2
D
1, 2T/C3
6
1, 3D
M1
D
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
logic symbol, each flip-flop
R
R
Q1
Q1
Q2
TE
G2
1, 2T/C3
CLK
D
1, 3D
M1
Q2
LOAD
logic diagram, each flip-flop (positive logic)
R
TE
(Toggle
Enable)
Q1
Q2
CLK
D
LOAD
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
typical clear, preset, count, and inhibit sequences
The following timing sequence is illustrated below:
1. Clear outputs to zero
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
Async
Clear
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
CC
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
V
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
20
T
A
0
70
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 4.75 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
I = –18 mA
–1.2
V
IK
I
I
I
I
= – 1 mA
= – 1 mA
= 20 mA
2.5
2.7
3.4
0.3
OH
OH
OL
V
OH
OL
0.5
0.1
V
I
I
V = 7 V
I
mA
µA
I
IH
V = 2.7 V
I
20
ENP, CLK, A, B, C, D
ENT, LOAD
CLR
– 0.6
– 1.2
– 0.6
–150
55
I
V
= 5.5 V,
V = 0.5 V
mA
IL
CC
I
§
I
I
V
V
= 5.5 V,
= 5.5 V
V = 0
O
–60
mA
mA
OS
CC
CC
37
CC
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
Clock frequency
Pulse duration
100
0
90
MHz
clock
CLK high or low (loading)
CLK (counting)
5
5
4
High
Low
4
ns
ns
w
6
7
CLR low
5
5
Data before CLK↑
High or low
High
5
5
11
8.5
11
5
11.5
9.5
11.5
5
LOAD before CLK↑
t
su
Setup time
Low
High
ENP and ENT before CLK↑
Data after CLK↑
Low
High or low
High
2
2
2
2
t
t
Hold time
ns
ns
LOAD after CLK↑
h
Low
0
0
ENP and ENT after CLK↑
High or low
0
0
†
Inactive-state setup time, CLR high before CLK↑
6
6
su
†
Inactive-state setup time also is referred to as recovery time.
switching characteristics (see Note 4)
V
= 5 V,
= 50 PF,
= 500 Ω,
= 25°C
V
= 4.5 V TO 5.5 V,
CC
CC
C
R
C
L
R
L
= 50 PF,
= 500Ω,
L
L
FROM
PARAMETER
TO
(OUTPUT)
UNIT
(INPUT)
‡
T
T
= MIN TO MAX
A
A
MIN
100
2.7
2.7
3.2
3.2
4.2
4.2
1.7
1.7
4.7
3.7
TYP
MAX
MIN
90
MAX
f
t
t
t
t
t
t
t
t
120
5.1
7.1
5.6
5.6
9.6
9.6
4.1
4.1
8.6
7.6
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
7.5
10
2.7
2.7
3.2
3.2
4.2
4.2
1.7
1.7
4.7
3.7
8.5
11
CLK (LOAD high)
CLK (LOAD low)
CLK
Any Q
Any Q
RCO
8.5
8.5
14
9.5
9.5
15
ns
ns
ns
ns
14
15
7.5
7.5
12
8.5
8.5
13
ENT
CLR
RCO
Any Q
RCO
t
PHL
10.5
11.5
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 4: Load circuits and waveforms are shown in Figure 1.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
7 V
Open
S1
500 Ω
From Output
Under Test
C
TEST
S1
From Output
Under Test
Test
Point
t
t
/t
Open
7 V
PLH PHL
/t
C
L
t
L
PLZ PZL
/t
500 Ω
500 Ω
(see Note A)
(see Note A)
Open
7 V
PHZ PZH
Open Collector
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
1.5 V
Timing Input
0 V
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
0 V
t
t
PLZ
PZL
t
t
t
PHL
PLH
Output
Waveform 1
S1 at 7 V
≈3.5 V
V
V
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
+ 0.3 V
OL
V
OL
(see Note B)
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
Out-of-Phase
Output
V
– 0.3 V
OH
1.5 V
1.5 V
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns,
O
r
f
duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
SN74F161AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74F161ADBR
SN74F161ADBRE4
SN74F161ADBRG4
SN74F161ADE4
SN74F161ADG4
SN74F161ADR
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
DB
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74F161ADRE4
SN74F161ADRG4
SN74F161AN
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74F161AN3
SN74F161ANE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
16
16
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74F161ANSR
SN74F161ANSRE4
SN74F161ANSRG4
ACTIVE
ACTIVE
ACTIVE
SO
SO
SO
NS
NS
NS
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
16
SN74F161ADBR
SN74F161ADR
DB
D
16
16
MLA
FMX
8.2
6.5
6.6
2.5
2.1
12
8
16
16
Q1
Q1
330
16
10.3
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74F161ADBR
SN74F161ADR
DB
D
16
16
MLA
FMX
346.0
342.9
346.0
336.6
33.0
28.58
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
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representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
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相关型号：
SN74F162AD
Decade Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, PDSO16, SOP-16
ROCHESTER
SN74F162AN
F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16, PLASTIC, DIP-16
TI
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