SN74F175N [TI]
QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR; 翻两番D型触发器与Clear型号: | SN74F175N |
厂家: | TEXAS INSTRUMENTS |
描述: | QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR |
文件: | 总5页 (文件大小:75K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54F175, SN74F175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993
SN54F175 . . . J PACKAGE
SN74F175 . . . D OR N PACKAGE
(TOP VIEW)
• Contain Four Flip-Flops With Double-Rail
Outputs
• Buffered Clock and Direct Clear Inputs
• Applications Include:
Buffer/Storage Registers
Shift Registers
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
CC
4Q
4Q
4D
3D
3Q
3Q
CLK
Pattern Generators
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
SN54F175 . . . FK PACKAGE
(TOP VIEW)
These monolithic, positive-edge-triggered flip-
flops utilize TTL circuitry to implement D-type
flip-flop logic with a direct clear (CLR) input.
Information at the data (D) inputs meeting setup
time requirements is transferred to outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the clock (CLK) input
is at either the high or low level, the D-input signal
has no effect at the output.
3
2
1
20 19
18
4Q
4D
NC
3D
3Q
1Q
1D
NC
2D
2Q
4
5
6
7
8
17
16
15
14
9 10 11 12 13
The SN54F175 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F175 is characterized for
operation from 0°C to 70°C.
NC – No internal connection
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
L
CLK
D
X
H
L
Q
L
Q
H
L
X
↑
H
H
L
H
↑
H
H
L
X
Q
Q
0
0
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F175, SN74F175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993
†
logic symbol
1
R
CLR
9
CLK
C1
2
3
1Q
1Q
4
1D
1D
7
2Q
2Q
3Q
5
6
2D
10
11
15
14
12
3D
3Q
4Q
13
4D
4Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
CLR
9
CLK
4
2
3
1D
1D
C1
1Q
1Q
R
Two Identical Channels
Not Shown
13
15
14
4D
1D
4Q
4Q
C1
R
Pin numbers shown are for the D, J, and N packages.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F175, SN74F175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Operating free-air temperature range: SN54F175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
SN74F175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
SN54F175
SN74F175
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
0.8
–18
– 1
0.8
–18
– 1
20
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
20
T
A
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54F175
SN74F175
PARAMETER
TEST CONDITIONS
UNIT
V
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 4.75 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
I = –18 mA
I
–1.2
–1.2
IK
I
I
I
= – 1 mA
= – 1 mA
= 20 mA
2.5
3.4
0.3
2.5
2.7
3.4
0.3
OH
OH
OL
V
OH
OL
0.5
0.1
0.5
0.1
V
I
I
I
I
I
V = 7 V
I
mA
µA
I
V = 2.7 V
I
20
20
IH
V = 0.5 V
I
– 0.6
–150
34
– 0.6
–150
34
mA
mA
mA
IL
§
V
O
= 0
–60
–60
OS
CC
See Note 2
22.5
22.5
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2:
I
is measured with outputs open with 4.5 V applied to all data inputs after a momentary ground followed by 4.5 V applied to CLK.
CC
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F175, SN74F175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
SN54F175
SN74F175
UNIT
′F175
MIN
0
MAX
MIN
0
MAX
100
MIN
0
MAX
100
f
t
Clock frequency
Pulse duration
100
MHz
ns
clock
CLK high
CLK low
4
4
4
5
5
5
w
CLR low
5
5
5
High or low
CLR high
High or low
3
3
3
Setup time, data before CLK↑
t
t
ns
ns
su
†
5
5
5
Setup time, inactive state, data before CLK↑
Hold time, data after CLK↑
1
1
1
h
†
Inactive-state setup time is also referred to as recovery time.
switching characteristics (see Note 3)
V
C
R
= 5 V,
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
CC
L
L
= 50 pF,
= 500 Ω,
= 25°C
= 500Ω,
= MIN to MAX
FROM
(INPUT)
TO
(OUTPUT)
‡
PARAMETER
UNIT
T
A
T
A
′F175
TYP
140
4.6
SN54F175
SN74F175
MIN
100
3.2
3.2
3.2
3.7
MAX
MIN
100
2.7
3.2
3.2
3.7
MAX
MIN
100
3.2
3.2
3.2
3.7
MAX
f
MHz
ns
max
PLH
PHL
PLH
PHL
t
t
t
t
6.5
8.5
8.5
10.5
10
7.5
9.5
9
CLK
CLR
Q or Q
6.1
6.1
8.5
Q
Q
ns
8.6
11.5
15
13
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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