SN74F193AD [TI]

SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR; 同步4位向上/向下二进制计数器,具有双时钟和CLEAR
SN74F193AD
型号: SN74F193AD
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER WITH DUAL CLOCK AND CLEAR
同步4位向上/向下二进制计数器,具有双时钟和CLEAR

计数器 时钟
文件: 总10页 (文件大小:275K)
中文:  中文翻译
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SN74F193A  
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER  
WITH DUAL CLOCK AND CLEAR  
SDFS031A – D3693, JANUARY 1991 – REVISED OCTOBER 1993  
D OR N PACKAGE  
(TOP VIEW)  
High-Speed f  
of 100 MHz Typical  
max  
Parallel Asynchronous Load for Modulo-N  
Count Lengths  
V
A
B
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
Look-Ahead Circuitry Enhances Speed of  
Q
B
A
Cascaded Counters  
CLR  
BO  
CO  
LOAD  
C
Q
Fully Synchronous in Count Modes  
Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
DOWN  
UP  
Q
Q
C
D
D
GND  
description  
The SN74F193A is a synchronous, 4-bit binary up/down counter. Synchronous counting operation is provided  
by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so  
instructed by the steering logic. This mode of operation eliminates the output counting spikes normally  
associated with asynchronous (ripple-clock) counters.  
The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count/clock (UP or  
DOWN) input. The direction of the count is determined by which count input is pulsed while the other count input  
is high.  
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on  
the LOAD input and entering the desired data at the data (D) inputs. The output will change to agree with the  
data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers  
by simply modifying the count length with the preset inputs.  
A high level applied to the clear (CLR) input forces all outputs to the low level. The clear function is independent  
of the count and load inputs.  
These counters were designed to be cascaded without the need for external circuitry. The borrow (BO) output  
produces a low-level pulse while the count is zero (all Q outputs low) and the DOWN input is low. Similarily, the  
carry (CO) output produces a low-level pulse while the count is 15 (all Q outputs high) and the UP input is low.  
The counters can then be easily cascaded by feeding the borrow and carry outputs to the count-down and  
count-up inputs, respectively, of the succeeding counter.  
The SN74F193A is characterized for operation from 0°C to 70°C.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F193A  
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER  
WITH DUAL CLOCK AND CLEAR  
SDFS031A – D3693, JANUARY 1991 – REVISED OCTOBER 1993  
logic symbol  
state diagram  
CTRDIV16  
CT = 0  
0
1
2
3
4
5
14  
CLR  
5
12  
13  
1CT = 15  
CO  
BO  
UP  
2+  
G1  
1–  
G2  
15  
4
DOWN  
2CT = 0  
11  
14  
13  
12  
6
7
8
C3  
LOAD  
15  
3
2
6
7
Q
A
A
1
3D  
Q
B
B
10  
C
9
Q
C
11  
10  
9
Q
D
D
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Count up  
Count down  
2–2  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F193A  
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER  
WITH DUAL CLOCK AND CLEAR  
SDFS031A – D3693, JANUARY 1991 – REVISED OCTOBER 1993  
logic diagram (positive logic)  
14  
12  
CLR  
CO  
13  
11  
BO  
LOAD  
5
UP  
4
DOWN  
S
R
15  
A
S
C1  
3
Q
A
1D  
R
1
B
S
2
Q
B
C1  
1D  
R
10  
C
S
6
Q
C
C1  
1D  
R
9
D
S
7
Q
D
C1  
1D  
R
2–3  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F193A  
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER  
WITH DUAL CLOCK AND CLEAR  
SDFS031A – D3693, JANUARY 1991 – REVISED OCTOBER 1993  
typical clear, load, and count sequence  
Illustrated below is the following sequence:  
1. Clear outputs to zero  
2. Load (preset) to binary thirteen  
3. Count up to fourteen, fifteen (carry), zero, one, and two  
4. Count down to one, zero (borrow), fifteen, fourteen, and thirteen  
CLR  
LOAD  
A
B
Data  
Inputs  
C
D
UP  
DOWN  
Q
A
Q
B
Q
C
Q
D
Outputs  
CO  
BO  
0
13  
14  
15  
0
1
2
1
0
15  
14  
13  
Sequence  
Illustrated  
Count Up  
Count Down  
Clear  
Preset  
2–4  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F193A  
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER  
WITH DUAL CLOCK AND CLEAR  
SDFS031A – D3693, JANUARY 1991 – REVISED OCTOBER 1993  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V  
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA  
Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V  
CC  
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA  
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 °C to 70 °C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: The input-voltage ratings may be exceeded if the input-current ratings are observed.  
recommended operating conditions  
MIN NOM  
MAX  
UNIT  
V
V
V
V
Supply voltage  
4.5  
2
5
5.5  
CC  
IH  
IL  
High-level input voltage  
Low-level input voltage  
Input clamp current  
V
0.8  
18  
– 1  
20  
70  
V
I
I
I
mA  
mA  
mA  
°C  
IK  
High-level output current  
Low-level output current  
Operating free-air temperature  
OH  
OL  
T
A
0
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
PARAMETER  
TEST CONDITIONS  
I = – 18 mA  
MIN TYP  
MAX  
UNIT  
V
V
V
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 4.5 V,  
= 4.5 V,  
= 4.75 V,  
= 4.5 V,  
= 5.5 V,  
= 5.5 V,  
– 1.2  
V
IK  
I
I
I
I
= – 1 mA  
2.5  
2.7  
3.4  
0.3  
OH  
OH  
OL  
V
OH  
OL  
= – 1 mA to 3 mA  
= 20 mA  
0.5  
0.1  
V
I
I
V = 7 V  
I
mA  
µA  
I
IH  
V = 2.7 V  
I
20  
UP  
– 1.8  
– 0.6  
– 150  
54  
I
V
= 5.5 V,  
V = 0.5 V  
mA  
IL  
CC  
I
Others  
§
I
I
V
V
= 5.5 V,  
= 5.5 V,  
V = 0  
O
– 60  
mA  
mA  
OS  
CC  
CC  
Outputs open  
34  
CC  
§
All typical values are at V  
= 5 V, T = 25°C.  
A
CC  
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.  
2–5  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F193A  
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER  
WITH DUAL CLOCK AND CLEAR  
SDFS031A – D3693, JANUARY 1991 – REVISED OCTOBER 1993  
timing requirements over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted)  
V
T
= 5 V,  
= 25°C  
V
= 4.5 V to 5.5 V,  
CC  
A
CC  
T = MIN to MAX  
A
UNIT  
MIN  
0
MAX  
MIN  
0
MAX  
85  
f
t
Clock frequency  
Pulse duration  
85  
MHz  
clock  
CLR high  
4
4
LOAD low  
5.5  
4
5.5  
4
ns  
w
UP or DOWN high  
UP or DOWN low  
6
6
Data before LOAD inactive  
CLR inactive before UPor DOWN↑  
LOAD inactive before UPor DOWN↑  
Data after LOAD inactive  
3.5  
5
3.5  
5
t
t
Setup time  
Hold time  
ns  
ns  
su  
7.5  
2.5  
7.5  
2.5  
h
switching characteristics (see Note 2)  
V
C
R
= 5 V,  
V
C
R
= 4.5 V to 5.5 V,  
= 50 pF,  
CC  
L
L
CC  
L
L
= 50 pF,  
= 500 ,  
= 25°C  
FROM  
PARAMETER  
TO  
(OUTPUT)  
= 500 ,  
= MIN to MAX  
UNIT  
(INPUT)  
T
A
T
A
MIN  
85  
2.5  
3
TYP  
MAX  
MIN  
85  
2.5  
3
MAX  
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
100  
MHz  
ns  
max  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
8.5  
8
9
9
UP or DOWN  
UP or DOWN  
A, B, C, or D  
CO or BO  
Any Q  
2.5  
5
8.5  
12  
2.5  
5
9
ns  
ns  
ns  
13  
8
2
7
1.5  
5
Any Q  
6
13.5  
10  
15  
11  
4.5  
5.5  
5
4
Any Q  
LOAD  
12  
5
13  
12  
13  
12  
15  
13.8  
14  
13.5  
Any Q  
CO  
11  
5
ns  
ns  
ns  
CLR  
CLR  
6
12  
5.5  
5
BO  
5
11  
6
13.5  
12.6  
13  
6
LOAD  
CO or BO  
CO or BO  
6
6
5.5  
4.5  
5
A, B, C, or D  
ns  
12.5  
4.5  
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.  
NOTE 2: Load circuits and waveforms are shown in Section 1.  
2–6  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
30-Mar-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
SOIC  
SOIC  
PDIP  
Drawing  
SN74F193AD  
SN74F193ADR  
SN74F193AN  
OBSOLETE  
OBSOLETE  
OBSOLETE  
D
D
N
16  
16  
16  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
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does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
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amplifier.ti.com  
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Copyright 2006, Texas Instruments Incorporated  

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