SN74F2373_10 [TI]
25-ohm OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS;
| 型号： | SN74F2373_10 |
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TEXAS INSTRUMENTS |
| 描述： | 25-ohm OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS 输出元件 |
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SN74F2373
25-Ω OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDFS100 – JANUARY 1996
DB, DW, OR N PACKAGE
(TOP VIEW)
Eight Latches in a Single Package
3-State True Outputs With 25-Ω Sink
Resistors
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
Full Parallel Access for Loading
Buffered Control Inputs
8Q
8D
7D
7Q
6Q
6D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB) Packages, and Plastic (N) DIPs
description
13 5D
12 5Q
11 LE
This 8-bit latch features 3-state outputs designed
to sink up to 12 mA, and include 25-Ω sink resitors
to reduce overshoot and undershoot.
GND 10
The eight latches of the SN74F2373 are transparent D-type latches. While the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When the LE is taken low, the Q outputs are latched at the logic levels
set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal
logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability
to drive bus lines without need for interface or pullup components.
OE input does not affect the internal operations of the latches. Old data can be retained or new data can be
entered while the outputs are in the high-impedance state.
The SN74F373 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN74F373 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F2373
25-Ω OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDFS100 – JANUARY 1996
†
logic symbol
logic diagram (positive logic)
1
1
OE
LE
EN
C1
OE
11
11
LE
3
2
5
1D
2D
3D
4D
5D
6D
7D
8D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
4
C1
2
1Q
7
6
3
1D
1D
8
9
13
14
17
18
12
15
16
19
To Seven Other Channels
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
schematic diagram
V
CC
Q
25 Ω
(nominal)
Typical Output Configuration
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F2373
25-Ω OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDFS100 – JANUARY 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
Input current range, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
I
Voltage range applied to any output in the disabled or power-off state, V . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Voltage range applied to any output in the high state, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Current into any output in the low state, I
Operating free-air temperature range,T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, T
O
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded if the input current ratings are observed.
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
V
0.8
–18
– 3
12
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
T
A
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
IK
V
V
V
V
= 4.5 V,
= 4.5 V
= 4.75 V,
= 4.5 V
–1.2
V
CC
CC
CC
CC
I
I
I
I
I
I
= – 1 mA
= – 3 mA
= -1 mA to – 3 mA
= 1 mA
2.5
2.4
2.7
3.4
OH
OH
OH
OL
OL
V
OH
3.3
V
0.2
0.5
0.5
0.75
50
V
OL
V
= 12 mA
I
I
I
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
O
V
O
= 2.7 V
µA
µA
OZ(H)
= 0.5 V
–50
0.1
OZ(L)
V = 7 V
I
mA
µA
I
V = 2.7 V
I
20
IH
IL
V = 0.5 V
I
– 0.6
–150
55
mA
mA
mA
mA
§
V
O
= 0
–60
OS
See Note 2, Condition A
See Note 2, Condition B
See Note 2, Condition C
38
46
43
CC(H)
CC(L)
CC(Z)
66
V
CC
= 5.5 V,
62
mA
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2:
I
is measured with the outputs open under the following conditions:
CC
A. OE at ground (0) and all other inputs at 4.5 V.
B. LE at 4.5 V and all other inputs grounded.
C. OE at 4.5 V and all other inputs grounded.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F2373
25-Ω OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDFS100 – JANUARY 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
MIN
MAX
UNIT
MIN
6
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
6
2
6
ns
ns
ns
2
5
switching characteristics (see Figure 1)
V
= 5 V,
= 50 PF,
= 500 Ω,
= 500 Ω,
= 25°C
V
= 4.5 V TO 5.5 V, C
L
CC
CC
= 50 PF,
C
R
R
L
1
2
R
R
T
A
= 500Ω,
FROM
PARAMETER
TO
(OUTPUT)
1
2
UNIT
= 500Ω,
= MIN TO MAX
(INPUT)
†
T
A
MIN
2.2
1.2
4.2
2.2
1.2
1.2
1.2
1.2
TYP
4.4
4.1
7.3
4.2
4.1
6
MAX
MIN
2.1
1.2
4.2
2.2
1.2
1.2
1.2
1.2
MAX
t
t
t
t
t
t
t
t
7
5.5
11.5
7
9
7
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
ns
ns
ns
ns
Q
Q
Q
13
8
LE
11
12
9.5
7.5
6
OE
8.3
6.5
6
4.2
3.5
OE
Q
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74F2373
25-Ω OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDFS100 – JANUARY 1996
PARAMETER MEASUREMENT INFORMATION
7 V (t
, t
, O.C.)
PZL PLZ
Open
(all others)
From Output
Under Test
Test
Point
S1
C
L
R1
(see Note A)
R1
From Output
Under Test
Test
Point
C
L
R2
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
(see Note A)
R
= R1 = R2
L
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note C)
3 V
0 V
1.5 V
1.5 V
t
w
3 V
3 V
0 V
Timing Input
(see Note C)
1.5 V
Low-Level
Pulse
1.5 V
1.5 V
0 V
3 V
0 V
t
h
t
su
VOLTAGE WAVEFORMS
PULSE DURATION
Data Input
(see Note C)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
Output
Control
1.5 V
1.5 V
(low-level enable)
0 V
3 V
Input
(see Note C)
t
PZL
1.5 V
1.5 V
t
PLZ
0 V
3.5 V
t
Waveform 1
(see Notes B and E)
PHL
t
PLH
In-Phase
Output
(see Note E)
V
OL
1.5 V
1.5 V
1.5 V
t
V
0.3 V
t
OL
PHZ
t
PZH
PLH
t
V
PHL
OH
0.3 V
0 V
V
OH
Waveform 2
(see Notes B and E)
Out-of-Phase
Output
(see Note E)
1.5 V
1.5 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, t = t ≤ 2.5 ns, duty cycle = 50%.
r
f
D. When measuring propagation delay times of 3-state outputs, switch S1 is open.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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