SN74F299D [TI]
IC,SHIFT REGISTER,F-TTL,SOP,20PIN,PLASTIC;
| 型号： | SN74F299D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,SHIFT REGISTER,F-TTL,SOP,20PIN,PLASTIC 存储 输出元件 |
| 文件： | 总13页 (文件大小：520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢆ ꢇ ꢀ ꢁꢈ ꢃꢄ ꢅꢆꢆ
ꢉ ꢊꢋꢌ ꢍ ꢎꢁꢌ ꢏꢐ ꢑꢀꢒꢓ ꢀꢔ ꢌꢄ ꢍꢕ ꢀꢍꢖ ꢑꢒꢗ ꢐ ꢑꢐꢗ ꢌ ꢀ ꢍꢐ ꢑꢀ
ꢘ ꢌꢍ ꢔ ꢙ ꢊꢀꢍꢒꢍ ꢐ ꢖ ꢎꢍ ꢚ ꢎꢍꢀ ꢛ
ꢛ
The SN54F299 is obsolete and no
longer supplied.
SDFS071B − MARCH 1987 − REVISED APRIL 2004
SN54F299 . . . J PACKAGE
SN74F299 . . . DW, N, OR NS PACKAGE
(TOP VIEW)
D Four Modes of Operation:
− Hold (Store)
− Shift Right
− Shift Left
− Load Data
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S0
OE1
OE2
V
CC
S1
SL
Q
D Operates With Outputs Enabled or at High
Impedance
G/Q
G
H′
D 3-State Outputs Drive Bus Lines Directly
D Can Be Cascaded for N-Bit Word Lengths
D Direct Overriding Clear
E/Q
H/Q
E
H
C/Q
F/Q
C
F
A/Q
Q
D/Q
B/Q
A
D
A′
B
D Applications:
CLR
GND
CLK
SR
− Stacked or Pushdown Registers
− Buffer Storage
− Accumulator Registers
SN54F299 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
These 8-bit universal shift/storage registers
feature multiplexed I/O ports to achieve full 8-bit
data handling in a single 20-pin package. Two
function-select (S0, S1) inputs and two
output-enable (OE1, OE2) inputs can be used to
choose the modes of operation listed in the
function table.
3
2
1
20 19
18
G/Q
SL
Q
4
5
6
7
8
G
E/Q
C/Q
17
E
H′
16 H/Q
C
H
A/Q
15
14
F/Q
A
F
Q
D/Q
A′
D
9 10 11 12 13
Synchronous parallel loading is accomplished by
taking both S0 and S1 high. This places the
3-state outputs in a high-impedance state and
permits data that is applied on the I/O ports to
be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in
any mode. Clearing occurs when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs
but has no effect on clearing, shifting, or storage of data.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
SN74F299N
SN74F299N
SN74F299DW
SN74F299DWR
SN74F299NSR
0°C to 70°C
SOIC − DW
SOP − NS
F299
74F299
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢆ ꢇ ꢀꢁ ꢈꢃ ꢄ ꢅꢆ ꢆ
ꢉꢊ ꢋꢌ ꢍ ꢎ ꢁꢌ ꢏ ꢐꢑ ꢀꢒ ꢓ ꢀ ꢔꢌ ꢄꢍ ꢕ ꢀꢍꢖ ꢑꢒꢗ ꢐ ꢑꢐ ꢗ ꢌꢀ ꢍꢐ ꢑꢀ
ꢘꢌ ꢍ ꢔ ꢙ ꢊꢀꢍꢒꢍ ꢐ ꢖ ꢎꢍꢚ ꢎꢍ ꢀꢛ
ꢛ
The SN54F299 is obsolete and no
longer supplied.
SDFS071B − MARCH 1987 − REVISED APRIL 2004
FUNCTION TABLE
INPUTS
MODE
I/O PORTS
OUTPUTS
†
†
OE2
CLR S1 S0 OE1
CLK SL SR A/Q
B/Q
C/Q
D/Q
E/Q
F/Q
G/Q
H/Q
Q
Q
A
B
C
D
E
F
G
H
A′
H′
L
L
L
X
L
H
L
X
H
L
L
X
L
L
X
X
X
X
X
X
X
X
X
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
L
L
L
L
Clear
Hold
H
H
L
X
L
X
L
L
L
L
X
L
X
X
X
X
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
A0
A0
B0
B0
C0
C0
D0
D0
E0
E0
F0
F0
G0
G0
H0
H0
A0
A0
H0
H0
Shift
Right
H
H
L
L
H
H
L
L
L
L
↑
↑
X
X
H
L
H
L
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
H
L
Q
Q
An
An
Bn
Bn
Cn
Cn
Dn
Dn
En
En
Fn
Fn
Gn
Gn
Gn
Gn
Shift
Left
H
H
H
H
L
L
L
L
L
L
↑
↑
H
L
X
X
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
H
L
Q
Q
H
L
Bn
Bn
Cn
Cn
Dn
Dn
En
En
Fn
Fn
Gn
Gn
Hn
Hn
Bn
Bn
Load
H
H
H
X
X
↑
X
X
a
b
c
d
e
f
g
h
a
h
NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop
outputs are isolated from the I/O terminals.
†
When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the register is not affected.
logic diagram (positive logic)
1
S0
19
S1
18
SL
(shift left
serial input)
11
SR
(shift right
Six
serial input)
Identical
Channels
Not
‡
Shown
12
CLK
1D
C1
1D
C1
R
R
8
17
Q
Q
A′
H′
9
CLR
2
OE1
3
OE2
7
16
H/Q
A/Q
A
H
‡
I/O ports not shown: B/Q (13), C/Q (6), D/Q (14), E/Q (5), F/Q (15), and G/Q (4).
B
C
D
E
F
G
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢆ ꢇ ꢀ ꢁꢈ ꢃꢄ ꢅꢆꢆ
ꢉ ꢊꢋꢌ ꢍ ꢎꢁꢌ ꢏꢐ ꢑꢀꢒꢓ ꢀꢔ ꢌꢄ ꢍꢕ ꢀꢍꢖ ꢑꢒꢗ ꢐ ꢑꢐꢗ ꢌ ꢀ ꢍꢐ ꢑꢀ
ꢘ ꢌꢍ ꢔ ꢙ ꢊꢀꢍꢒꢍ ꢐ ꢖ ꢎꢍ ꢚ ꢎꢍꢀ ꢛ
ꢛ
The SN54F299 is obsolete and no
longer supplied.
SDFS071B − MARCH 1987 − REVISED APRIL 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA
Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
Current into any output in the low state: Q or Q
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
A′
H′
SN54F299 (Q thru Q ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
SN74F299 (Q thru Q ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
A
H
A
H
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54F299
SN74F299
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
0.8
−18
− 1
− 3
20
0.8
−18
− 1
− 3
20
V
I
IK
mA
Q
Q
Q
Q
or Q
H′
A′
A
I
High-level output current
mA
OH
OL
thru Q
H
or Q
A′
A
H′
I
Low-level output current
mA
thru Q
20
24
H
T
A
Operating free-air temperature
−55
125
0
70
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢆ ꢇ ꢀꢁ ꢈꢃ ꢄ ꢅꢆ ꢆ
ꢉꢊ ꢋꢌ ꢍ ꢎ ꢁꢌ ꢏ ꢐꢑ ꢀꢒ ꢓ ꢀ ꢔꢌ ꢄꢍ ꢕ ꢀꢍꢖ ꢑꢒꢗ ꢐ ꢑꢐ ꢗ ꢌꢀ ꢍꢐ ꢑꢀ
ꢘꢌ ꢍ ꢔ ꢙ ꢊꢀꢍꢒꢍ ꢐ ꢖ ꢎꢍꢚ ꢎꢍ ꢀꢛ
ꢛ
The SN54F299 is obsolete and no
longer supplied.
SDFS071B − MARCH 1987 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54F299
SN74F299
PARAMETER
TEST CONDITIONS
I = −18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
CC
= 4.5 V,
−1.2
−1.2
V
IK
I
Q
Q
or Q
H′
I
I
I
I
I
I
I
= − 1 mA
= − 1 mA
2.5
2.5
2.4
3.4
3.4
3.3
2.5
2.5
2.4
2.7
3.4
3.4
3.3
A′
OH
OH
OH
OH
OL
OL
OL
V
= 4.5 V
CC
CC
thru Q
H
V
V
OH
A
= − 3 mA
Any output
V
= 4.75 V,
= − 1 mA to −3 mA
= 20 mA
Q
or Q
H′
0.3
0.3
0.5
0.5
0.3
0.5
A′
= 20 mA
V
OL
V
CC
= 4.5 V
Q
thru Q
A
H
= 24 mA
0.35
0.5
1
A thru H
Any other
A thru H
Any other
A thru H
S0 or S1
Any other
V = 5.5 V
1
0.1
I
I
I
V
V
= 5.5 V
= 5.5 V,
mA
I
CC
V = 7 V
I
0.1
70
70
‡
V = 2.7 V
I
µA
IH
CC
20
20
−0.65
−1.2
−0.6
−150
95
−0.65
−1.2
−0.6
−150
95
‡
I
IL
V
CC
= 5.5 V,
V = 0.5 V
I
mA
§
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 0
O
−60
−60
mA
mA
OS
CC
CC
See Note 4
68
68
CC
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
For I/O ports (Q thru Q ), the parameters I and I include the off-state output current.
A
H
IH
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
is measured with OE1, OE2, and CLK at 4.5 V.
IL
NOTE 4: I
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
SN54F299
SN74F299
UNIT
′F299
MIN
MAX
MIN
MAX
65
MIN
MAX
70
f
t
Clock frequency
Pulse duration
70
MHz
ns
clock
CLK high or low
CLR low
7
7
8
8
7
7
w
S0 or S1
High or low
High or low
8.5
5.5
9.5
6.5
8.5
5.5
Setup time before
CLK↑
A/Q thru H/Q , SR, or SL
A
H
t
ns
ns
su
h
Inactive-state setup
time before CLK↑
CLR
High
7
13
7
¶
S0 or S1
A/Q thru H/Q , SR, or SL
High or low
High or low
0
2
0
2
0
2
Hold time after CLK↑
t
A
H
¶
Inactive-state setup time also is referred to as recovery time.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢆ
ꢛ
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ꢋ
ꢌ
ꢍ
ꢎ
ꢁ
ꢌ
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ꢘ ꢌꢍ ꢔ ꢙ ꢊꢀꢍꢒꢍ ꢐ ꢖ ꢎꢍ ꢚ ꢎꢍꢀ ꢛ
ꢗ
ꢐ
ꢑ
ꢐ
ꢗ
ꢌ
ꢀ
ꢍ
ꢐ
ꢑ
ꢀ
The SN54F299 is obsolete and no
longer supplied.
SDFS071B − MARCH 1987 − REVISED APRIL 2004
switching characteristics (see Figure 1)
V
= 5 V,
V
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
CC
L
L
C
R
T
= 50 pF,
= 500 Ω,
= 25°C
C
R
T
= 500 Ω,
FROM
(INPUT)
TO
(OUTPUT)
†
= MIN to MAX
PARAMETER
UNIT
A
A
′F299
TYP
100
6.6
SN54F299
SN74F299
MIN
70
MAX
MIN
65
MAX
MIN
70
MAX
f
MHz
ns
max
PLH
PHL
PLH
PHL
t
t
t
t
3.2
2.7
3.2
4.2
3.7
5.7
2.7
3.2
1.7
1.2
9
8.5
9
2.7
2.2
2.7
3.7
3.2
5
10.5
10
3.2
2.7
3.2
4.2
3.7
5.7
2.7
3.2
1.7
1.2
10
9.5
10
12
10.5
15
9
CLK
CLK
Q
Q
or Q
H′
A′
6.1
6.6
11
thru Q
or Q
ns
ns
A
H
8.1
11
9.5
14
8
12.5
11.5
15.5
10.5
12
7.1
Q
A′
H′
CLR
t
PHL
10.6
5.6
Q
thru Q
A
H
t
t
2.2
2.7
1.7
1.2
PZH
OE1 or OE2
OE1 or OE2
Q
thru Q
ns
ns
A
H
H
t
6.6
10
6
11
PZL
4.1
9
7
PHZ
Q
thru Q
A
t
3.6
5.5
7.5
6.5
PLZ
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢆ ꢇ ꢀꢁ ꢈꢃ ꢄ ꢅꢆ ꢆ
ꢉꢊ ꢋꢌ ꢍ ꢎ ꢁꢌ ꢏ ꢐꢑ ꢀꢒ ꢓ ꢀ ꢔꢌ ꢄꢍ ꢕ ꢀꢍꢖ ꢑꢒꢗ ꢐ ꢑꢐ ꢗ ꢌꢀ ꢍꢐ ꢑꢀ
ꢘꢌ ꢍ ꢔ ꢙ ꢊꢀꢍꢒꢍ ꢐ ꢖ ꢎꢍꢚ ꢎꢍ ꢀꢛ
ꢛ
The SN54F299 is obsolete and no
longer supplied.
SDFS071B − MARCH 1987 − REVISED APRIL 2004
PARAMETER MEASUREMENT INFORMATION
7 V
S1
Open
500 Ω
TEST
S1
From Output
Under Test
C
Test
Point
From Output
Under Test
t
t
/t
Open
7 V
PLH PHL
/t
C
t
L
L
PLZ PZL
/t
500 Ω
500 Ω
(see Note A)
(see Note A)
Open
7 V
PHZ PZH
Open Collector
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
Timing Input
1.5 V
0 V
t
w
t
h
t
3 V
su
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
Input
3 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
0 V
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
≈3.5 V
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
OL
+ 0.3 V
− 0.3 V
V
OL
OL
(see Note B)
t
PHZ
t
PHL
PLH
t
PZH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
Out-of-Phase
Output
V
OH
1.5 V
1.5 V
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns,
O
r
f
duty cycle = 50%.
D. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
SN74F299DW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
20
20
20
20
20
20
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74F299DWG4
SN74F299DWR
SN74F299DWRE4
SN74F299DWRG4
SN74F299N
SOIC
SOIC
SOIC
SOIC
PDIP
DW
DW
DW
DW
N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74F299N3
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
20
20
TBD
Call TI
Call TI
SN74F299NE4
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74F299NSR
SN74F299NSRE4
SN74F299NSRG4
ACTIVE
ACTIVE
ACTIVE
SO
SO
SO
NS
NS
NS
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74F299DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 20
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
SN74F299DWR
2000
Pack Materials-Page 2
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