SN74F657DW [TI]

OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS; 带奇偶校验生成器/校验和三态输出的八路收发器
SN74F657DW
型号: SN74F657DW
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
带奇偶校验生成器/校验和三态输出的八路收发器

输出元件
文件: 总10页 (文件大小:229K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN74F657  
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER  
AND 3-STATE OUTPUTS  
SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993  
DW OR NT PACKAGE  
Combines F245 and F280B Functions in  
(TOP VIEW)  
One Package  
High-Impedance N-P-N Inputs for Reduced  
Loading (70 µA in Low and High States)  
T/R  
A1  
A2  
A3  
A4  
A5  
OE  
B1  
B2  
B3  
B4  
GND  
GND  
B5  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
High Output Drive and Light Bus Loading  
3-State B Outputs Sink 64 mA and Source  
15 mA  
Input Diodes for Termination Effects  
Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
V
CC  
A6  
A7  
B6  
A8 10  
15 B7  
ODD/EVEN  
ERR  
B8  
PARITY  
11  
12  
14  
13  
description  
The SN74F657 contains eight noninverting  
buffers with 3-state outputs and an 8-bit parity  
generator/checker. It is intended for bus-oriented  
applications. The buffers have a specified current  
sinking capability of 24 mA at the A port and 64 mA  
at the B port.  
The transmit/receive (T/R) input determines the direction of the data flow through the bidirectional transceivers.  
When T/R is high, data is transmitted from the A port to the B port. When T/R is low, data is received at the A port  
from the B port.  
When the output enable (OE) input is high, both the A and B ports are placed in a high-impedance state  
(disabled). The ODD/EVEN input allows the user to select between odd or even parity systems. When  
transmitting from A port to B port (T/R high), PARITY is an output from the generator/checker. When receiving  
from B port to A port (T/R low), PARITY is an input.  
When transmitting (T/Rhigh), theparityselect(ODD/EVEN) input is made high or low as appropriate. The A port  
is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by  
ODD/EVEN and the number of high bits on A port. When ODD/EVEN is low (for even parity) and the number  
of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port  
is even, the PARITY will be low, keeping even parity.  
When in the receive mode (T/R low), the B port is polled to determine the number of high bits. If ODD/EVEN  
is low (for even parity) and the number of highs on B port is:  
1. Odd and the PARITY input is high, then ERR will be high signifying no error.  
2. Even and the PARITY input is high, then ERR will be low indicating an error.  
The SN74F657 is characterized for operation from 0°C to 70°C.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F657  
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER  
AND 3-STATE OUTPUTS  
SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993  
FUNCTION TABLE  
INPUTS  
T/R ODD/EVEN  
OUTPUTS  
NUMBER OF A OR B  
INPUTS THAT ARE HIGH  
INPUT/OUTPUT  
PARITY  
OE  
L
ERR  
Z
OUTPUT MODE  
Transmit  
Transmit  
Receive  
Receive  
Receive  
Receive  
Transmit  
Transmit  
Receive  
Receive  
Receive  
Receive  
Z
H
H
L
H
L
H
L
L
Z
L
H
H
L
H
L
H
L
0, 2, 4, 6, 8  
L
L
L
L
H
L
L
L
L
L
H
Z
L
H
H
L
H
L
L
L
H
H
L
Z
L
H
H
L
L
1, 3, 5, 7  
L
L
H
H
L
L
L
H
L
L
L
L
Don’t care  
H
X
X
Z
Z
logic symbol  
24  
OE  
G3  
1
T/R  
3 EN1/3G5 [REC]  
3 EN2 [XMIT]  
N4  
11  
2
ODD/EVEN  
A1  
23  
1
1
B1  
Z11  
2
3
22  
21  
20  
17  
16  
15  
14  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
4
5
6
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
2 k  
13  
12  
4, 2  
5
PARITY  
ERR  
4, 1  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
2–2  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F657  
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER  
AND 3-STATE OUTPUTS  
SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993  
logic diagram (positive logic)  
1
T/R  
24  
2
OE  
A1  
23  
B1  
22  
3
B2  
A2  
4
21  
A3  
B3  
5
20  
A4  
B4  
17  
6
B5  
A5  
8
16  
A6  
B6  
15  
9
A7  
B7  
10  
14  
A8  
B8  
13  
11  
PARITY  
ODD/EVEN  
12  
ERR  
2–3  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F657  
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER  
AND 3-STATE OUTPUTS  
SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
CC  
Input voltage range, V (excluding I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 V to 7 V  
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA to 5 mA  
Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V  
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V  
CC  
Current into any output in the low state: A1A8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA  
B1B8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA  
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: The input-voltage ratings may be exceeded provided the input-current ratings are observed.  
recommended operating conditions  
MIN NOM  
MAX  
UNIT  
V
V
V
Supply voltage  
4.5  
2
5
5.5  
V
V
V
CC  
IH  
IL  
High-level input voltage  
Low-level input voltage  
0.8  
– 3  
– 12  
24  
A1A8  
I
High-level output current  
mA  
OH  
OL  
B1B8, PARITY, ERR  
A1A8  
I
Low-level output current  
mA  
B1B8, PARITY, ERR  
64  
T
A
Operating free-air temperature  
0
70  
°C  
2–4  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F657  
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER  
AND 3-STATE OUTPUTS  
SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
PARAMETER  
TEST CONDITIONS  
I = – 18 mA  
MIN TYP  
MAX  
UNIT  
V
IK  
V
V
V
V
= 4.5 V,  
= 4.5 V,  
= 4.5 V,  
= 4.75 V,  
– 1.2  
V
CC  
CC  
CC  
CC  
I
Any output  
B1B8, PARITY, ERR  
Any output  
A1A8  
I
I
I
I
I
= – 3 mA  
2.4  
2
3.3  
3.1  
OH  
OH  
OH  
OL  
OL  
= – 15 mA  
= – 1 mA to – 3 mA  
= 24 mA  
V
OH  
V
V
2.7  
0.35  
0.42  
0.5  
0.55  
0.1  
V
OL  
V
CC  
= 4.5 V  
= 64 mA  
B1B8, PARITY, ERR  
T/R  
V
CC  
V
CC  
V
CC  
= 0,  
= 0,  
= 0,  
V = 7 V,  
I
OE = 4.5 V  
T/R = 4.5 V  
OE  
V = 7 V,  
I
0.1  
I
I
ODD/EVEN  
A1A8  
V = 7 V  
I
0.1  
mA  
2
V
CC  
= 5.5 V,  
V = 7 V  
I
B1B8  
1
A, B, PARITY  
T/R, OE  
70  
V
= 5.5 V,  
V = 2.7 V  
I
40  
µA  
I
I
CC  
IH  
ODD/EVEN  
A, B, PARITY  
T/R, OE  
20  
– 70  
– 40  
– 20  
– 150  
– 225  
50  
V
V
= 5.5 V,  
= 5.5 V,  
V = 0.5 V  
I
µA  
CC  
IL  
ODD/EVEN  
A1A8  
– 60  
V
O
= 0  
mA  
CC  
§
– 100  
B1B8  
I
I
I
I
I
I
OS  
ERR  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 5.5 V,  
= 5.5 V,  
= 5.5 V  
= 5.5 V  
= 5.5 V  
V = 2.7 V  
I
µA  
µA  
OZH  
OZL  
CCH  
CCL  
ERR  
V = 0.5 V  
I
50  
125  
150  
145  
90  
106  
98  
mA  
mA  
mA  
CCZ  
§
All typical values are at V  
For I/O ports, the parameters I and I include the off-state output current.  
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.  
= 5 V, T = 25°C.  
A
CC  
IH  
IL  
2–5  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN74F657  
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER  
AND 3-STATE OUTPUTS  
SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993  
switching characteristics (see Note 2)  
V
C
= 5 V,  
= 50 pF,  
V
= 4.5 V to 5.5 V,  
C = 50 pF,  
L
CC  
L
CC  
R1 = 500 ,  
R1 = 500 ,  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
R2 = 500 ,  
R2 = 500 ,  
T = MIN to MAX  
A
T
= 25°C  
TYP  
4.2  
A
MIN  
2.5  
3
MAX  
7.5  
7.5  
14  
MIN  
2.5  
3
MAX  
t
t
t
t
t
t
t
t
t
t
8
8
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PZH  
A or B  
A
B or A  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
4
6
8.4  
6
16  
PARITY  
PARITY, ERR  
ERR  
6.8  
4
8.5  
15  
6.8  
4
16  
6.4  
11  
12  
ODD/EVEN  
4.5  
8
6.9  
11.5  
20.5  
20.5  
15.5  
15.5  
8
4.5  
7.5  
7.5  
6
12.5  
22.5  
22.5  
16.5  
17  
12.7  
13.4  
8.1  
B
PARITY  
OE  
8
6
ERR  
7.5  
3
8.8  
7.5  
3
t
5.3  
9
A, B, PARITY, or ERR  
t
4
5.4  
9.5  
7.5  
6
4
11  
PZL  
PHZ  
t
2
4.2  
2
8
OE  
A, B, PARITY, or ERR  
t
2
3.7  
2
6.5  
PLZ  
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.  
These delay times reflect the 3-state recovery time only and not the signal through the buffers or parity check circuitry. To assure valid information  
at the ERR output pin, time must be allowed for the signal to propagate through the drivers (B to A), and to the ERR output. Valid data at the ERR  
output is greater than or equal to (B to A) + (A to PARITY).  
NOTE 2: Load circuits and waveforms are shown in Section 1.  
2–6  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
30-Mar-2005  
PACKAGING INFORMATION  
Orderable Device  
SN74F657DW  
SN74F657DWR  
SN74F657NT  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOIC  
DW  
24  
24  
24  
25  
2000  
15  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-250C-1 YEAR/  
Level-1-235C-UNLIM  
SOIC  
PDIP  
DW  
NT  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-250C-1 YEAR/  
Level-1-235C-UNLIM  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MPDI004 – OCTOBER 1994  
NT (R-PDIP-T**)  
PLASTIC DUAL-IN-LINE PACKAGE  
24 PINS SHOWN  
A
PINS **  
24  
28  
DIM  
24  
13  
1.260  
(32,04) (36,20)  
1.425  
A MAX  
1.230  
(31,24) (35,18)  
1.385  
A MIN  
B MAX  
B MIN  
0.280 (7,11)  
0.250 (6,35)  
0.310  
(7,87)  
0.315  
(8,00)  
1
12  
0.290  
(7,37)  
0.295  
(7,49)  
0.070 (1,78) MAX  
B
0.020 (0,51) MIN  
0.200 (5,08) MAX  
Seating Plane  
0.125 (3,18) MIN  
0.100 (2,54)  
0.010 (0,25)  
0°15°  
0.021 (0,53)  
0.015 (0,38)  
M
0.010 (0,25) NOM  
4040050/B 04/95  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
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Post Office Box 655303 Dallas, Texas 75265  
Copyright 2005, Texas Instruments Incorporated  

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ZXFV4089

VIDEO AMPLIFIER WITH DC RESTORATION

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ZETEX

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