SN74GTLP817 [TI]
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER; GTLP - TO- LVTTL 1 - TO- 6扇出驱动器
| 型号： | SN74GTLP817 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER |
| 文件： | 总15页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
www.ti.com
SCES285E–OCTOBER 1999–REVISED APRIL 2005
FEATURES
DGV, DW, OR PW PACKAGE
(TOP VIEW)
•
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
AI
AO1
GNDT
OEAB
1
2
3
4
5
6
7
8
9
24
23
•
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
GNDT
AO2
22 BO1
•
•
•
•
•
GTLP-to-LVTTL 1-to-6 Fanout Driver
LVTTL-to-GTLP 1-to-2 Fanout Driver
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
GNDG
21
20
19
18
V
CC
V
REF
AO3
GNDT
AO4
GNDG
ERC
17 BO2
16 GNDG
15 BI
Reduced-Drive LVTTL Outputs
(–12 mA/12 mA)
V
CC
AO5 10
GNDT
AO6
•
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for Optimal
Data-Transfer Rate and Signal Integrity in
Distributed Loads
OEBA
GNDT
11
12
14
13
•
•
•
•
Ioff and Power-Up 3-State Support Hot
Insertion
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
The SN74GTLP817 is a medium-drive fanout driver that provides LVTTL-to-GTLP and GTLP-to-LVTTL
signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic
levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL
or LVTTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold
levels, improved differential input, and OEC™ circuitry. The improved GTLP OEC circuitry minimizes bus settling
time and has been designed and tested using several backplane models. The medium drive allows incident-wave
switching in heavily loaded backplanes with equivalent load impedance down to 19 Ω. BO1 and BO2 can be tied
together to drive an equivalent load impedance down to 11 Ω.
GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLP817 is given only at the preferred higher noise-margin GTLP,
but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP
(VTT = 1.5 V and VREF = 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
GNDT is the TTL output ground, while GNDG is the GTLP output ground, and both may be separated from each
other for a quieter device.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
www.ti.com
SCES285E–OCTOBER 1999–REVISED APRIL 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
This device features adjustable edge-rate control (ERC). Changing the ERC input voltage between GND and VCC
adjusts the B-port output rise and fall times. This allows the designer to optimize system data-transfer rate and
signal integrity to the backplane load. ERC automatically is selected to the same speed as alternate source
1-to-6 fanout drivers that use pin 18 for 3.3-V or 5-V VCC
.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74GTLP817DW
TOP-SIDE MARKING
GTLP817
Tube
SOIC – DW
Tape and reel
SN74GTLP817DWR
SN74GTLP817PWR
SN74GTLP817DGVR
–40°C to 85°C
TSSOP – PW
TVSOP – DGV
Tape and reel
Tape and reel
GT817
GT817
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
<BR/>
FUNCTIONAL DESCRIPTION
The SN74GTLP817 is a fanout driver providing LVTTL-to-GTLP translation and GTLP-to-LVTTL translation in the
same package.
The LVTTL-to-GTLP direction is a 1-to-2 fanout driver with a single output enable (OEAB).
The GTLP-to-LVTTL direction is a 1-to-6 fanout driver with a single output enable (OEBA).
Data polarity is inverting for both directions.
2
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
www.ti.com
SCES285E–OCTOBER 1999–REVISED APRIL 2005
FUNCTION TABLES
OUTPUT CONTROL
(A TO B)
INPUTS
OEAB
OUTPUT
BOn
MODE
AI
X
H
L
L
Z
L
Isolation
H
L
Inverted transparent
H
OUTPUT CONTROL
(B TO A)
INPUTS
OUTPUT
AOn
MODE
BI
X
OEBA
H
L
L
Z
L
Isolation
H
L
Inverted transparent
H
B-PORT EDGE-RATE CONTROL (ERC)
INPUT ERC
OUTPUT
B-PORT
EDGE RATE
LOGIC
LEVEL
NOMINAL
VOLTAGE
VCC
H
L
Slow
Fast
GND
LOGIC DIAGRAM (POSITIVE LOGIC)
23
OEAB
ERC
18
22
BO1
GTLP Outputs
1
17
(LVTTL Input) AI
BO2
14
2
OEBA
AO1
4
AO2
AO3
6
8
15
20
BI (GTLP Input)
LVTTL Outputs
V
REF
AO4
AO5
10
12
AO6
3
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
www.ti.com
SCES285E–OCTOBER 1999–REVISED APRIL 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
4.6
UNIT
VCC
Supply voltage range
–0.5
V
|VGNDG – VGNDT
|
Ground dc voltage difference
0.3
7
V
AI port and control inputs
BI port and VREF
AO port
–0.5
–0.5
–0.5
–0.5
VI
Input voltage range(2)
V
4.6
7
Voltage range applied to any output in the
high-impedance or power-off state(2)
VO
V
BO port
4.6
24
AO port
IO
IO
Current into any output in the low state
mA
BO port
100
24
Current into any A output in the high state(3)
Continuous current through each VCC or GND
Input clamp current
mA
mA
mA
mA
±100
–50
–50
86
IIK
VI < 0
IOK
Output clamp current
VO < 0
DGV package
DW package
PW package
θJA
Package thermal impedance(4)
46
°C/W
°C
88
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
4
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
www.ti.com
SCES285E–OCTOBER 1999–REVISED APRIL 2005
Recommended Operating Conditions(1)(2)(3)(4)
MIN
3.15
1.14
1.35
0.74
0.87
NOM
3.3
1.2
1.5
0.8
1
MAX
3.45
1.26
1.65
0.87
1.1
UNIT
VCC
VTT
Supply voltage
V
GTL
GTLP
GTL
GTLP
BI
Termination voltage
V
V
V
VREF
Reference voltage
Input voltage
VTT
VI
AI, OE
BI
VCC
5.5
VREF + 0.05
VCC – 0.6
2
VIH
High-level input voltage
Low-level input voltage
ERC
AI, OE
BI
VCC
5.5
V
V
VREF – 0.05
VIL
ERC
AI, OE
GND
0.6
0.8
–18
–12
12
IIK
Input clamp current
mA
mA
IOH
High-level output current
AO port
AO port
IOL
Low-level output current
mA
BO port
50
∆t/∆v
∆t/∆VCC
TA
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
ns/V
µs/V
°C
20
Operating free-air temperature
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Normal connection sequence is GND first and VCC = 3.3 V, I/O, control inputs, VTT, VREF (any order) last.
(3) VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
(4) VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT
.
5
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
www.ti.com
SCES285E–OCTOBER 1999–REVISED APRIL 2005
Electrical Characteristics
over recommended operating free-air temperature range for GTLP (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
VIK
VCC = 3.15 V,
II = –18 mA
IOH = –100 µA
IOH = –100 µA
IOH = –6 mA
IOH = –12 mA
IOL = 100 µA
IOL = 100 µA
IOL = 6 mA
–1.2
V
VCC = 3.15 V to 3.45 V,
VCC – 0.2
VCC – 0.2
2.4
VOH
AO port
V
VCC = 3.15 V
2.2
VCC = 3.15 V to 3.45 V,
VCC = 3.15 V
0.2
0.2
0.4
0.5
0.2
0.5
0.55
±5
AO port
BO port
VOL
IOL = 12 mA
IOL = 100 µA
IOL = 40 mA
IOL = 50 mA
VI = 0 or 5.5 V
VO = VCC
V
VCC = 3.15 V
VCC = 3.45 V
II
BI, AI, OE, ERC VCC = 3.45 V,
µA
µA
AO port
BO port
AO port
BO port
10
IOZH
VO = 1.5 V
5
VO = GND
–10
–5
IOZL
VCC = 3.45 V
µA
VO = 5.5 V
Outputs high
Outputs low
Outputs disabled
10
VCC = 3.45 V, IO = 0,
VI (AI or control input) = VCC or GND,
VI (BI input) = VTT or GND
ICC
AO or BO port
10
mA
10
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND
(2)
∆ICC
AI, OE
1
mA
pF
AI, OE, ERC
BI
VI = VCC or 0
VI = VTT or 0
VO = VCC or 0
VO = VTT or 0
4
3.5
4
4.4
3.9
4.5
5.4
Ci
AO port
BO port
Co
pF
5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the increase in supply current for each input that is at the specified LVTTL voltage level, rather than VCC or GND.
Hot-Insertion Specifications for A Port
over recommended operating free-air temperature range
PARAMETER
Ioff
TEST CONDITIONS
VI or VO = 0 to 5.5 V
VO = 0.5 V to 3 V,
MIN
MAX
10
UNIT
µA
VCC = 0,
IOZPU
VCC = 0 to 1.5 V,
VCC = 1.5 V to 0,
OE = 0
OE = 0
±30
±30
µA
IOZPD
VO = 0.5 V to 3 V,
µA
Hot-Insertion Specifications for B Port
over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
10
UNIT
µA
Ioff
VCC = 0,
VI or VO = 0 to 1.5 V
VO = 0.5 V to 1.5 V,
VO = 0.5 V to 1.5 V,
IOZPU
IOZPD
VCC = 0 to 1.5 V,
VCC = 1.5 V to 0,
OE = 0
OE = 0
±30
±30
µA
µA
6
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
www.ti.com
SCES285E–OCTOBER 1999–REVISED APRIL 2005
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
EDGE RATE(1)
MIN TYP(2) MAX
UNIT
tPLH
tPHL
tPLH
tPHL
ten
3
1.8
2
6
4.7
5
AI
BO
BO
BO
BO
Slow
ns
AI
Fast
Slow
Fast
ns
ns
ns
ns
ns
ns
ns
1.5
3
4.2
6.1
4.7
6
OEAB
OEAB
tdis
2
ten
2.1
1.5
tdis
4.7
Slow
Fast
Slow
Fast
2.5
1.4
1.7
1
tr
tf
Rise time, B outputs (20% to 80%)
Fall time, B outputs (80% to 20%)
tPLH
tPHL
ten
2.3
1.9
1.1
1.2
6
4.7
6.3
5
BI
AO
AO
OEBA
tdis
(1) Slow (ERC = VCC) and Fast (ERC = GND)
(2) All typical values are at VCC = 3.3 V, TA = 25°C.
7
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
www.ti.com
SCES285E–OCTOBER 1999–REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
1.5 V
25 Ω
6 V
Open
GND
S1
500 Ω
From Output
Under Test
TEST
/t
S1
Open
6 V
From Output
Under Test
Test
Point
t
t
PLH PHL
t
/t
C = 50 pF
PLZ PZL
L
500 Ω
/t
GND
(see Note A)
PHZ PZH
C = 30 pF
L
(see Note A)
LOAD CIRCUIT FOR AO PORTS
LOAD CIRCUIT FOR BO PORTS
3 V
0 V
1.5 V
1.5 V
Input
t
t
PHL
PLH
V
V
OH
1 V
1 V
Output
3 V
Output
Control
OL
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(AI to BO port)
0 V
3 V
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
1.5 V
0 V
1.5 V
1 V
1 V
V
OL
+ 0.3 V
Input
V
(see Note B)
OL
OH
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
V
OH
− 0.3 V
1.5 V
1.5 V
1.5 V
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(AO ports)
PROPAGATION DELAY TIMES
(BI to AO port)
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
8
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
www.ti.com
SCES285E–OCTOBER 1999–REVISED APRIL 2005
Distributed-Load Backplane Switching Characteristics
The preceding switching characteristics table shows the switching characteristics of the device into a lumped
load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical
representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a
resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum
performance in this RLC circuit. The following switching characteristics table shows the switching characteristics
of the device into the RLC load, to help the designer better understand the performance of the GTLP device in
this typical backplane. See www.ti.com/sc/gtlp for more information.
1.5 V
1.5 V
Z
O
= 70 Ω
0.25”
2”
2”
0.25”
Conn.
Conn.
Conn.
Conn.
1”
1”
1”
1”
Rcvr
Rcvr
Rcvr
Drvr
Slot 1
Slot 2
Slot 9
Slot 10
Figure 2. Medium-Drive Test Backplane
1.5 V
19 Ω
L = 19 nH
L
From Output
Under Test
Test
Point
C = 9 pF
L
Figure 3. Medium-Drive RLC Network
9
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
www.ti.com
SCES285E–OCTOBER 1999–REVISED APRIL 2005
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
EDGE RATE(1)
TYP(2)
UNIT
tPLH
tPHL
tPLH
tPHL
ten
4.4
4.4
3.2
3.2
4
AI
BO
BO
BO
BO
Slow
ns
AI
Fast
Slow
Fast
ns
ns
ns
ns
ns
OEAB
OEAB
tdis
4.4
2.9
3.1
1.8
1
ten
tdis
Slow
Fast
Slow
Fast
tr
tf
Rise time, B outputs (20% to 80%)
2
Fall time, B outputs (80% to 20%)
1.6
(1) Slow (ERC = VCC) and Fast (ERC = GND)
(2) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
10
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jun-2005
PACKAGING INFORMATION
Orderable Device
SN74GTLP817DGVR
SN74GTLP817DGVRE4
SN74GTLP817DW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TVSOP
DGV
24
24
24
24
24
24
24
24
24
24
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
TVSOP
SOIC
DGV
DW
DW
DW
DW
PW
PW
PW
PW
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74GTLP817DWE4
SN74GTLP817DWR
SN74GTLP817DWRE4
SN74GTLP817PW
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
60
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
SN74GTLP817PWE4
SN74GTLP817PWR
SN74GTLP817PWRE4
60
Pb-Free
(RoHS)
2000
2000
Pb-Free
(RoHS)
Pb-Free
(RoHS)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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