SN74GTLPH16945DGGR [TI]
GTLP SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, PLASTIC, TSSOP-48;
| 型号： | SN74GTLPH16945DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | GTLP SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, PLASTIC, TSSOP-48 总线收发器 |
| 文件： | 总13页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
DGG OR DGV PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1A1
1A2
GND
1A3
1A4
1OE
1B1
1B2
GND
1B3
1B4
BIAS V
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
2
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
3
4
5
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
6
7
V
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
LVTTL Outputs (–24 mA/24 mA)
CC
CC
8
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
I
, Power-Up 3-State, and BIAS V
CC
off
Support Live Insertion
Bus Hold on A-Port Data Inputs
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
V
V
CC
REF
2A5
2A6
GND
2A7
2A8
2B5
2B6
GND
2B7
2B8
2OE
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
description
2DIR
The SN74GTLPH16945 is a medium-drive, 16-bit
bustransceiverthatprovidesLVTTL-to-GTLPand
GTLP-to-LVTTL signal-level translation. It is
partitioned as two 8-bit transceivers. The device
provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times
faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP’s reduced output swing
(<1 V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry.
Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using
several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with
equivalent load impedance down to 19 Ω.
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLPH16945 is given only at the preferred higher noise margin GTLP, but the
user has the flexibility of using this device at either GTL (V = 1.2 V and V
= 0.8 V) or GTLP (V = 1.5 V
TT
REF
TT
and V
= 1 V) signal levels.
REF
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
reference voltage.
is the B-port differential input
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
description (continued)
This device is fully specified for live-insertion applications using I , power-up 3-state, and BIAS V . The I
off
off
CC
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
circuitry precharges and preconditions the B-port
CC
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves
signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
GQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
A
B
C
D
E
F
1DIR
1A2
1A4
1A6
2A8
2A1
2A3
2A5
2A7
2DIR
NC
NC
NC
NC
1OE
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2OE
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
GND
GND
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
V
CC
BIAS V
CC
GND
GND
G
H
J
GND
GND
G
H
J
V
CC
V
REF
GND
NC
GND
K
NC
K
NC – No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
†
T
PACKAGE
A
MARKING
GTLPH16945
GL945
TSSOP – DGG
Tape and reel
Tape and reel
Tape and reel
SN74GTLPH16945GR
SN74GTLPH16945VR
SN74GTLPH16945KR
–40°C to 85°C TVSOP – DGV
VFBGA – GQL
GL945
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
functional description
The SN74GTLPH16945 is a medium-drive (50 mA), 16-bit bus transceiver partitioned as two 8-bit segments
and is designed for asynchronous communication between data buses. The device transmits data from the
A port to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR)
input. OE can be used to disable the device so the buses are effectively isolated. Data polarity is noninverting.
For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When
OE is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to that of A to B, except OE and DIR are low.
FUNCTION TABLE
INPUTS
OUTPUT
MODE
Isolation
OE
H
DIR
X
Z
L
L
B data to A port
A data to B port
True transparent
L
H
logic diagram (positive logic)
1
1DIR
48
47
1OE
1B1
2
1A1
31
V
REF
To Seven Other Channels
24
2DIR
25
36
2OE
2B1
13
2A1
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
and BIAS V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
CC
Input voltage range, V (see Note 1): A port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
B port and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
REF
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Current into any output in the low state, I : A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Current into any A port output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
Continuous current through each V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
IK
I
Output clamp current, I
OK
O
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
recommended operating conditions (see Notes 4 through 7)
MIN
NOM
MAX
UNIT
V
,
CC
BIAS V
Supply voltage
3.15
3.3
3.45
V
CC
GTL
1.14
1.35
0.74
0.87
1.2
1.5
0.8
1
1.26
1.65
0.87
1.1
V
V
V
V
V
Termination voltage
V
V
V
V
V
TT
REF
I
GTLP
GTL
Reference voltage
Input voltage
GTLP
B port
V
TT
5.5
Except B port
B port
V
CC
V
+0.05
REF
High-level input voltage
Low-level input voltage
IH
IL
Except B port
B port
2
V
–0.05
REF
Except B port
0.8
–18
–24
24
I
I
Input clamp current
mA
mA
IK
High-level output current
A port
OH
OL
A port
I
Low-level output current
mA
B port
50
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
ns/V
µs/V
°C
20
CC
T
A
Operating free-air temperature
–40
85
NOTES: 4. All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V
= 3.3 V first, I/O second, and
CC
V
CC
= 3.3 Vlast,becausetheBIASV
prechargecircuitryisdisabledwhenanyV
CC CC
pinisconnected.ThecontrolandV inputs
REF
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable, but generally, GND is connected first.
6.
7.
V
V
and R can be adjusted to accommodate backplane impedances if the dc recommended I
ratings are not exceeded.
can be adjusted to optimize noise margins, but normally is two-thirds V . TI-OPC circuitry is enabled in the A-to-B direction
TT
TT OL
REF
TT
and is activated when V > 0.7 V above V
minimize current drain.
. If operated in the A-to-B direction, V
should be set to within 0.6 V of V to
TT
TT
REF REF
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
= 3.15 V,
I = –18 mA
–1.2
V
IK
CC
I
= 3.15 V to 3.45 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –12 mA
= –24 mA
= 100 µA
= 12 mA
= 24 mA
= 100 µA
= 10 mA
= 40 mA
= 50 mA
V
CC
–0.2
CC
OH
OH
OH
OL
OL
OL
OL
OL
OL
OL
V
OH
A port
2.4
2
V
V
CC
V
CC
V
CC
V
CC
= 3.15 V
= 3.15 V to 3.45 V,
= 3.15 V
0.2
0.4
0.5
0.2
0.2
0.4
0.55
±10
10
A port
V
OL
= 3.15 V to 3.45 V,
V
B port
V
CC
= 3.15 V
I
I
V
V
= 3.45 V,
= 3.45 V
V = 0 or 5.5 V
I
µA
µA
Control inputs
CC
V
O
V
O
V
O
= V
CC
A port
‡
I
CC
OZH
= 1.5 V
= GND
10
B port
‡
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.45 V,
= 3.15 V,
= 3.15 V,
= 3.45 V,
= 3.45 V,
–10
µA
µA
µA
µA
µA
I
I
I
I
I
A and B ports
A port
OZL
BHL
BHH
§
V = 0.8 V
I
75
–75
¶
A port
V = 2 V
I
#
A port
V = 0 to V
500
BHLO
I
CC
CC
||
A port
V = 0 to V
I
–500
BHHO
Outputs high
Outputs low
50
50
50
V
= 3.45 V, I = 0,
O
CC
I
A or B port
mA
V (A-port or control input) = V
or GND,
CC
I
CC
V (B port) = V or GND
I
TT
Outputs disabled
V
= 3.45 V, One A-port or control input at V
– 0.6 V,
CC
CC
1.5
mA
pF
∆I
CC
Other A-port or control inputs at V
or GND
CC
C
C
Control inputs
A port
V = 3.15 V or 0
I
4.5
7.5
7.5
5
9
9
i
V
= 3.15 V or 0
= 1.5 V or 0
O
O
pF
io
B port
V
†
‡
§
All typical values are at V
For I/O ports, the parameters I
OZH
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
= 3.3 V, T = 25°C.
A
CC
and I
include the input leakage current.
OZL
should be measured after lowering V to GND and
BHL IN
IL
then raising it to V max.
IL
¶
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
An external driver must source at least I
An external driver must sink at least I
BHHO
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
#
||
to switch this node from low to high.
BHLO
to switch this node from high to low.
or GND.
CC
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
BIAS V = 0,
MIN
MAX
10
UNIT
µA
I
I
I
V
CC
V
CC
V
CC
= 0,
V or V = 0 to 5.5 V
I O
off
CC
= 0 to 1.5 V,
= 1.5 V to 0,
V
= 0.5 V to 3 V,
= 0.5 V to 3 V,
OE = 0
OE = 0
±30
±30
µA
OZPU
OZPD
O
O
V
µA
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
10
UNIT
µA
µA
µA
mA
µA
V
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0,
BIAS V
BIAS V
BIAS V
= 0,
= 0,
= 0,
V or V = 0 to 1.5 V
off
CC
CC
CC
I
O
= 0 to 1.5 V,
= 1.5 V to 0,
= 0 to 3.15 V
= 3.15 V to 3.45 V
= 0,
V
= 0.5 V to 1.5 V, OE = 0
±30
±30
5
OZPU
OZPD
O
O
V
= 0.5 V to 1.5 V, OE = 0
I
(BIAS V
CC
)
BIAS V
= 3.15 V to 3.45 V,
V
O
(B port) = 0 to 1.5 V
CC
CC
10
V
BIAS V
BIAS V
= 3.3 V,
I
O
= 0
0.95
1.05
O
CC
I
= 0,
= 3.15 V to 3.45 V,
V
O
(B port) = 0.6 V
–1
µA
O
CC
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTLP (see Figure 1)
TT
REF
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
2.1
2.1
2
6.3
6.3
6.9
6.9
PLH
PHL
en
A
B
B
ns
ns
OE
2
dis
r
Rise time, B outputs (20% to 80%)
Fall time, B outputs (80% to 20%)
2.5
2.1
ns
ns
f
2.1
2.1
0.3
0.3
5.3
5.3
5.7
5.7
PLH
PHL
en
B
A
A
ns
ns
OE
dis
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
PARAMETER MEASUREMENT INFORMATION
1.5 V
25 Ω
6 V
Open
GND
S1
500 Ω
From Output
Under Test
TEST
S1
Open
6 V
From Output
Under Test
Test
Point
t
t
t
/t
PLH PHL
/t
C
= 50 pF
L
500 Ω
PLZ PZL
/t
(see Note A)
C
= 30 pF
(see Note A)
L
GND
PHZ PZH
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
3 V
0 V
1.5 V
1.5 V
Input
t
t
PHL
PLH
V
V
OH
1 V
1 V
Output
3 V
OL
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
0 V
3 V
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
1.5 V
0 V
1 V
1 V
1.5 V
Input
V
OL
+ 0.3 V
(see Note B)
V
OL
OH
t
t
PHL
t
t
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
– 0.3 V
1.5 V
1.5 V
Output
1.5 V
V
OL
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16945
16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
SCES292D – OCTOBER 1999 – REVISED NOVEMBER 2001
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
1.5 V
1.5 V
Z
O
= 70 Ω
.25”
2”
2”
.25”
1.5 V
19 Ω
Conn.
Conn.
Conn.
Conn.
L
L
= 19 nH
From Output
Under Test
Test
Point
1”
1”
1”
1”
C
= 9 pF
L
Rcvr
Rcvr
Rcvr
Drvr
Slot 1
Slot 2
Slot 9
Slot 10
Figure 2. Medium-Drive Test Backplane
Figure 3. Medium-Drive RLC Network
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTLP (see Figure 3)
TT
REF
FROM
(INPUT)
TO
(OUTPUT)
†
TYP
PARAMETER
UNIT
t
t
t
t
t
t
4.3
4.3
5
PLH
PHL
en
dis
r
A
B
B
ns
ns
OE
4.4
1
Rise time, B outputs (20% to 80%)
Fall time, B outputs (80% to 20%)
ns
ns
2
f
†
All typical values are at V
= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.
CC
A
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
SN74GTLPH16945GR
SN74GTLPH16945VR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
TVSOP
DGV
48
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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