SN74GTLPH3245GKFR_技术文档

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

SCES291D – OCTOBER 1999 – REVISED FEBRUARY 2002

Member of the Texas Instruments

Widebus+ Family

Variable Edge-Rate Control (ERC) Input

Selects GTLP Rise and Fall Times for

Optimal Data-Transfer Rate and Signal

Integrity in Distributed Loads

TI-OPC Circuitry Limits Ringing on

Unevenly Loaded Backplanes

I

, Power-Up 3-State, and BIAS V

CC

off

OEC Circuitry Improves Signal Integrity

and Reduces Electromagnetic Interference

Support Live Insertion

Bus Hold on A-Port Data Inputs

Bidirectional Interface Between GTLP

Signal Levels and LVTTL Logic Levels

Distributed V

High-Speed Switching Noise

and GND Pins Minimize

CC

LVTTL Interfaces Are 5-V Tolerant

High-Drive GTLP Outputs (100 mA)

LVTTL Outputs (–24 mA/24 mA)

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

description

The SN74GTLPH3245 is a high-drive, 32-bit bus transceiver that provides LVTTL-to-GTLP and

GTLP-to-LVTTL signal-level translation. It is partitioned as four 8-bit transceivers. The device provides a

high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal

levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result

of GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC

circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have

been designed and tested using several backplane models. The high drive allows incident-wave switching in

heavily loaded backplanes with equivalent load impedance down to 11 Ω.

GTLP is the Texas Instruments (TI ) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard

JESD 8-3. The ac specification of the SN74GTLPH3245 is given only at the preferred higher noise-margin

GTLP, but the user has the flexibility of using this device at either GTL (V = 1.2 V and V

= 0.8 V) or GTLP

TT

REF

(V = 1.5 V and V

= 1 V) signal levels.

TT

REF

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,

but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V

reference voltage.

is the B-port differential input

REF

This device is fully specified for live-insertion applications using I , power-up 3-state, and BIAS V . The I

off

CC

circuitry disables the outputs, preventing damaging current backflow through the device when it is powered

down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power

down, which prevents driver conflict. The BIAS V

circuitry precharges and preconditions the B-port

CC

input/output connections, preventing disturbance of active data on the backplane during card insertion or

removal, and permits true live-insertion capability.

This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated

backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves

signal integrity, which allows adequate noise margin to be maintained at higher frequencies.

High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC

input voltage between GND and V

optimize system data-transfer rate and signal integrity to the backplane load.

adjusts the B-port output rise and fall times. This allows the designer to

CC

Active bus-hold circuitry is provided to hold unused or undriven LVTTL data inputs at a valid logic state. Use

of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

OEC, TI, TI-OPC, and Widebus+ are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

SCES291D – OCTOBER 1999 – REVISED FEBRUARY 2002

description (continued)

When V

is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.

CC

However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V

CC

through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of

the driver.

GKF PACKAGE

(TOP VIEW)

terminal assignments

1

2

3

4

5

6

1

2

3

4

5

1B2

6

A

B

C

D

E

F

A

B

C

D

E

F

1A3

GND

1A6

1A8

1ERC

2A2

2A4

GND

2A6

NC

1A2

1A4

1A5

1A7

GND

2A1

2A3

2A5

2A7

3A1

3A2

3A4

3A5

3A7

GND

4A1

4A3

4A5

4A7

1A1

1DIR

GND

1B1

1OE

GND

1B3

GND

1B6

1B8

1B4

1B5

1V

CC

1V

CC

1B7

GND

1BIAS V

2B1

1V

REF

CC

2B2

2B4

GND

2B6

NC

G

H

J

1V

CC

1V

CC

2B3

G

H

J

GND

2A8

GND

2B8

2B5

2B7

K

L

2DIR

3DIR

GND

2OE

3OE

GND

3B1

K

L

3A3

GND

3A6

3A8

2ERC

4A2

4A4

GND

4A6

3B2

3B3

GND

3B6

3B8

M

N

P

R

T

3B4

M

N

P

R

T

2V

CC

2V

CC

3B5

GND

3B7

2BIAS V

4B1

2V

REF

CC

2V

CC

2V

CC

4B2

4B4

GND

4B6

U

V

W

GND

4A8

GND

4B8

4B3

4B5

U

V

W

4DIR

4OE

4B7

NC – No internal connection

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

T

A

PACKAGE

–40°C to 85°C LFBGA – GKF

Tape and reel

SN74GTLPH3245GKFR

GM45

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

2

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SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

SCES291D – OCTOBER 1999 – REVISED FEBRUARY 2002

functional description

The SN74GTLPH3245 is a high-drive (100 mA), 32-bit bus transceiver partitioned in four 8-bit segments and

is designed for asynchronous communication between data buses. The device transmits data from the A port

to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input.

OE can be used to disable the device so the buses are effectively isolated. Data polarity is noninverting.

For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When

OE is high, the outputs are in the high-impedance state.

The data flow for B to A is similar to that of A to B, except OE and DIR are low.

Function Tables

OUTPUT CONTROL

INPUTS

OUTPUT

MODE

Isolation

OE

H

DIR

X

Z

L

B data to A port

A data to B port

True transparent

L

H

B-PORT EDGE-RATE CONTROL (ERC)

INPUT ERC

OUTPUT

B-PORT

EDGE RATE

LOGIC NOMINAL

LEVEL VOLTAGE

L

GND

Slow

Fast

H

V

CC

3

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SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

SCES291D – OCTOBER 1999 – REVISED FEBRUARY 2002

†

logic diagram (positive logic)

B3

1DIR

B4

1OE

E1

1ERC

A4

A3

1B1

1A1

E6

1V

REF

To Seven Other Channels

K3

F2

2DIR

2A1

K4

F5

2OE

2B1

To Seven Other Channels

are associated with these channels.

†

1V

CC

and 1BIAS V

CC

4

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SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

SCES291D – OCTOBER 1999 – REVISED FEBRUARY 2002

†

logic diagram (positive logic) (continued)

L3

3DIR

L4

K5

3OE

3B1

R1

K2

2ERC

3A1

R6

2V

REF

To Seven Other Channels

W3

T2

4DIR

4A1

W4

T5

4OE

4B1

To Seven Other Channels

are associated with these channels.

†

2V

CC

and 2BIAS V

CC

5

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SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

SCES291D – OCTOBER 1999 – REVISED FEBRUARY 2002

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

and BIAS V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V

CC

Input voltage range, V (see Note 1): A port, ERC, and control inputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

I

B port and V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V

REF

Voltage range applied to any output in the high-impedance or power-off state, V

O

(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V

Current into any output in the low state, I : A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA

O

B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Current into any A port output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA

O

Continuous current through each V

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA

CC

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA

Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36°C/W

IK

I

Output clamp current, I

OK

O

JA

stg

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and V > V

.

CC

O

3. The package thermal impedance is calculated in accordance with JESD 51-7.

6

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SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

SCES291D – OCTOBER 1999 – REVISED FEBRUARY 2002

recommended operating conditions (see Notes 4 through 7)

MIN

NOM

MAX

UNIT

V

,

CC

BIAS V

Supply voltage

3.15

3.3

3.45

V

CC

GTL

1.14

1.35

0.74

0.87

1.2

1.5

0.8

1

1.26

1.65

0.87

1.1

V

Termination voltage

V

TT

REF

I

GTLP

GTL

Reference voltage

Input voltage

GTLP

B port

V

TT

Except B port

V

5.5

CC

B port

V

+0.05

REF

V

High-level input voltage

Low-level input voltage

ERC

V

CC

–0.6

5.5

V

IH

IL

CC

Except B port and ERC

B port

2

V

–0.05

REF

V

ERC

GND

0.6

0.8

–18

–24

24

Except B port and ERC

I

Input clamp current

mA

IK

High-level output current

A port

OH

OL

A port

I

Low-level output current

mA

B port

100

10

∆t/∆v

∆t/∆V

Input transition rise or fall rate

Power-up ramp rate

Outputs enabled

ns/V

µs/V

°C

20

CC

T

A

Operating free-air temperature

–40

85

NOTES: 4. All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V

= 3.3 V first, I/O second, and

CC

V

CC

= 3.3 Vlast,becausetheBIASV

prechargecircuitryisdisabledwhenanyV

CC CC

pinisconnected.ThecontrolandV inputs

REF

can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection

sequence is acceptable, but generally, GND is connected first.

6.

7.

V

and R can be adjusted to accommodate backplane impedances if the dc recommended I

ratings are not exceeded.

can be adjusted to optimize noise margins, but normally is two-thirds V . TI-OPC circuitry is enabled in the A-to-B direction

TT

TT OL

REF

TT

and is activated when V > 0.7 V above V

minimize current drain.

. If operated in the A-to-B direction, V

should be set to within 0.6 V of V to

TT

REF REF

7

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SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

SCES291D – OCTOBER 1999 – REVISED FEBRUARY 2002

electrical characteristics over recommended operating free-air temperature range for GTLP

(unless otherwise noted)

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

V

= 3.15 V,

I = –18 mA

–1.2

V

IK

CC

I

= 3.15 V to 3.45 V,

I

= –100 µA

= –12 mA

= –24 mA

= 100 µA

= 12 mA

= 24 mA

= 10 mA

= 64 mA

= 100 mA

V

CC

–0.2

CC

OH

OL

V

OH

A port

2.4

2

V

CC

V

CC

V

CC

= 3.15 V

= 3.15 V to 3.45 V,

= 3.15 V

0.2

0.4

A port

0.5

V

OL

0.2

B port

V

= 3.15 V

= 3.45 V

0.4

CC

0.55

±10

±20

±10

V = 0 or V

I

A-port and

control inputs

CC

‡

I

V = 5.5 V

I

V

µA

V = 0 to 1.5 V

I

B port

A port

§

I

V

CC

V

CC

V

CC

V

CC

= 3.15 V,

= 3.45 V,

V = 0.8 V

I

75

–75

µA

BHL

¶

V = 2 V

I

BHH

#

A port

V = 0 to V

500

BHLO

I

CC

||

V = 0 to V

I

–500

BHHO

Outputs high

Outputs low

80

V

= 3.45 V, I = 0,

O

CC

I

A or B port

mA

V (A-port or control input) = V

or GND,

CC

I

CC

V (B port) = V or GND

I

TT

Outputs disabled

V

= 3.45 V, One A-port or control input at V

– 0.6 V,

CC

1.5

mA

pF

∆I

CC

Other A-port or control inputs at V

or GND

CC

C

Control inputs

A port

V = 3.15 V or 0

I

4

5

7.5

11

i

V

= 3.15 V or 0

= 1.5 V or 0

6.5

9.5

O

pF

io

B port

V

†

‡

§

All typical values are at V

= 3.3 V, T = 25°C.

A

I

CC

For I/O ports, the parameter I includes the off-state output leakage current.

The bus-hold circuit can sink at least the minimum low sustaining current at V max. I

then raising it to V max.

IL

The bus-hold circuit can source at least the minimum high sustaining current at V min. I

then lowering it to V min.

IH

An external driver must source at least I

An external driver must sink at least I

BHHO

This is the increase in supply current for each input that is at the specified TTL voltage level rather than V

should be measured after lowering V to GND and

IN

IL

BHL

¶

should be measured after raising V to V

IN

and

CC

IH

BHH

#

||

to switch this node from low to high.

BHLO

to switch this node from high to low.

or GND.

CC

hot-insertion specifications for A port over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

BIAS V = 0,

MIN

MAX

10

UNIT

µA

I

V

CC

V

CC

V

CC

= 0,

V or V = 0 to 5.5 V

I O

off

CC

= 0 to 1.5 V,

= 1.5 V to 0,

V

= 0.5 V to 3 V,

OE = 0

±30

µA

OZPU

OZPD

O

V

µA

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

SCES291D – OCTOBER 1999 – REVISED FEBRUARY 2002

live-insertion specifications for B port over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

MAX

10

UNIT

µA

mA

µA

V

I

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 0,

BIAS V

= 0,

V or V = 0 to 1.5 V

off

CC

I

O

= 0 to 1.5 V,

= 1.5 V to 0,

= 0 to 3.15 V

= 3.15 V to 3.45 V

= 0,

V

= 0.5 V to 1.5 V, OE = 0

±30

5

OZPU

OZPD

O

V

= 0.5 V to 1.5 V, OE = 0

I

(BIAS V

CC

)

BIAS V

= 3.15 V to 3.45 V,

V

O

(B port) = 0 to 1.5 V

CC

10

V

BIAS V

= 3.3 V,

I

O

= 0

0.95

1.05

O

CC

I

= 0,

= 3.15 V to 3.45 V,

V

O

(B port) = 0.6 V

–1

µA

O

CC

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, V = 1.5 V and V

= 1 V for GTLP (see Figure 1)

TT

REF

FROM

PARAMETER

TO

(OUTPUT)

†

‡

EDGE RATE

MIN TYP

MAX

UNIT

(INPUT)

t

3.9

3.1

2.6

2.1

4.1

4

7.2

8.4

5.7

5.8

7.3

9.4

5.9

6.9

PLH

PHL

PLH

PHL

en

A

B

Slow

Fast

Slow

Fast

ns

B

ns

OE

dis

2.9

4

en

dis

Slow

Fast

Slow

Fast

3

t

Rise time, B outputs (20% to 80%)

Fall time, B outputs (80% to 20%)

r

f

1.5

4

t

2.5

t

0.5

1.2

1.1

1.7

6.7

4.5

6.3

5.1

PLH

PHL

en

B

A

—

OE

dis

†

‡

Slow (ERC = GND) and Fast (ERC = V

)

CC

= 3.3 V, T = 25°C.

All typical values are at V

CC

A

9

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SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

SCES291D – OCTOBER 1999 – REVISED FEBRUARY 2002

PARAMETER MEASUREMENT INFORMATION

1.5 V

6 V

S1

Open

500 Ω

From Output

Under Test

12.5 Ω

From Output

Under Test

= 30 pF

GND

TEST

S1

Open

6 V

Test

Point

t

/t

C

= 50 pF

PLH PHL

L

500 Ω

t

/t

(see Note A)

PLZ PZL

/t

C

L

GND

PHZ PZH

(see Note A)

LOAD CIRCUIT FOR A OUTPUTS

LOAD CIRCUIT FOR B OUTPUTS

3 V

0 V

1.5 V

Input

t

PHL

PLH

V

OH

1 V

Output

3 V

OL

Output

Control

1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

(A port to B port)

0 V

3 V

t

PLZ

PZL

Output

Waveform 1

S1 at 6 V

1.5 V

0 V

1 V

1.5 V

Input

V

OL

+ 0.3 V

(see Note B)

V

OL

OH

t

PHL

t

PLH

PZH

PHZ

Output

Waveform 2

S1 at GND

V

OH

V

OH

– 0.3 V

1.5 V

Output

1.5 V

V

OL

≈0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

(B port to A port)

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

(A port)

NOTES: A.

C includes probe and jig capacitance.

L

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.

O

r

f

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

10

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SN74GTLPH3245

32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER

SCES291D – OCTOBER 1999 – REVISED FEBRUARY 2002

DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS

The preceding switching characteristics table shows the switching characteristics of the device into a lumped load

(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation

is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance

capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC

circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC

load, to help the designer better understand the performance of the GTLP device in this typical backplane. See

www.ti.com/sc/gtlp for more information.

1.5 V

Z

O

= 50 Ω

.25”

1”

.25”

11 Ω

Conn.

L

= 14 nH

From Output

Under Test

Test

Point

1”

Rcvr

C = 18 pF

L

Drvr

Slot 1

Slot 2

Slot 19

Slot 20

Figure 3. High-Drive RLC Network

Figure 2. High-Drive Test Backplane

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, V = 1.5 V and V

= 1 V for GTLP (see Figure 3)

TT

REF

FROM

(INPUT)

TO

(OUTPUT)

†

‡

TYP

PARAMETER

EDGE RATE

UNIT

t

4.9

3.7

5.1

5.4

4.1

2

PLH

PHL

PLH

PHL

en

A

B

Slow

ns

A

Fast

Slow

Fast

ns

OE

dis

en

dis

Slow

Fast

Slow

Fast

t

Rise time, B outputs (20% to 80%)

r

f

1.2

2.5

1.8

t

Fall time, B outputs (80% to 20%)

)

†

‡

Slow (ERC = GND) and Fast (ERC = V

All typical values are at V

CC

A

= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.

CC

11

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型号：	SN74GTLPH3245GKFR
厂家：	TEXAS INSTRUMENTS
描述：	GTLP SERIES, QUAD 8-BIT TRANSCEIVER, TRUE OUTPUT, PBGA114, PLASTIC, LFBGA-114 信息通信管理输出元件逻辑集成电路
文件：	总13页 (文件大小：261K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74GTLPH3245GKFR [TI]

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