SN74HC163PWTG4 [TI]
HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, GREEN, PLASTIC, TSSOP-16;
| 型号： | SN74HC163PWTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, GREEN, PLASTIC, TSSOP-16 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总27页 (文件大小：915K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
SN54HC163 . . . J OR W PACKAGE
SN74HC163 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
V
CC
RCO
Typical t = 14 ns
pd
4-mA Output Drive at 5 V
Q
Q
Q
Q
A
B
C
D
Low Input Current of 1 µA Max
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
B
C
D
ENP
GND
ENT
LOAD
Synchronously Programmable
SN54HC163 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting designs. The ’HC163
devices are 4-bit binary counters. Synchronous
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincident with each other when
instructed by the count-enable (ENP, ENT) inputs
and internal gating. This mode of operation
eliminates the output counting spikes normally
associated with synchronous (ripple-clock)
counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of
the clock waveform.
3
2
1
20 19
18
A
B
Q
Q
4
5
6
7
8
A
B
17
16
15
14
NC
C
NC
Q
Q
C
D
D
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube of 25
Tube of 40
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HC163N
SN74HC163N
SN74HC163D
SN74HC163DR
SN74HC163DT
SN74HC163NSR
SN74HC163DBR
SN74HC163PW
SN74HC163PWR
SN74HC163PWT
SNJ54HC163J
HC163
SOP − NS
HC163
HC163
−40°C to 85°C
SSOP − DB
TSSOP − PW
HC163
CDIP − J
CFP − W
LCCC − FK
SNJ54HC163J
SNJ54HC163W
SNJ54HC163FK
−55°C to 125°C
SNJ54HC163W
SNJ54HC163FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
ꢑ ꢘ ꢣ ꢛ ꢚꢦ ꢡꢠ ꢞꢟ ꢠꢚ ꢜꢣ ꢥꢗ ꢝꢘ ꢞ ꢞꢚ ꢭꢍ ꢮꢋ ꢕꢐ ꢯ ꢋꢈꢰꢂ ꢈꢂꢉ ꢝꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢝ ꢛ ꢢ ꢞꢢ ꢟꢞꢢ ꢦ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢊ ꢃ ꢄꢅꢆ ꢇ ꢈ
ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢅ ꢄ ꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁ ꢓꢐꢏ ꢅꢑ ꢒꢁ ꢎꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
description/ordering information (continued)
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR) input sets all four of
the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs.
This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
logic diagram (positive logic)
9
LOAD
10
ENT
15
RCO
†
LD
7
ENP
†
CK
2
CLK
1
CK
LD
CLR
R
M1
G2
14
13
1, 2T/1C3
G4
Q
Q
A
B
3
3D
4R
A
M1
G2
1, 2T/1C3
G4
3D
4R
4
B
M1
G2
12
1, 2T/1C3
Q
C
G4
3D
4R
5
C
M1
G2
11
1, 2T/1C3
Q
D
G4
3D
4R
6
D
†
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
3
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢊ ꢃ ꢄꢅꢆ ꢇ ꢈ
ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢅ ꢄ ꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁ ꢓꢐꢏ ꢅꢑ ꢒꢁ ꢎꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
logic symbol, each D/T flip-flop
LD (Load)
M1
G2
TE (Toggle Enable)
CK (Clock)
1, 2T/1C3
G4
Q (Output)
D (Inverted Data)
R (Inverted Reset)
3D
4R
logic diagram, each D/T flip-flop (positive logic)
CK
LD
TE
†
TG
TG
LD
TG
Q
TG
†
LD
†
CK
D
R
†
CK
TG
TG
†
†
CK
CK
†
The origins of LD and CK are shown in the logic diagram of the overall device.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (synchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
Async
Clear
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢅ ꢄ ꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁ ꢓꢐꢏ ꢅꢑ ꢒꢁ ꢎꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC163
MIN NOM
SN74HC163
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
‡
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
−55
−40
°C
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
‡
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
IL IH
= 2 V does not damage the device; however, functionally,
t
CC
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC163
SN74HC163
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
V
V
V = V or V
IH
V
OH
OL
I
IL
I
I
= −4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= −5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
8
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
V = V or V
V
I
IH
IL
I
I
= 4 mA
4.5 V
6 V
0.4
0.33
0.33
1000
80
OL
= 5.2 mA
0.4
OL
I
I
V = V
I
or 0
6 V
1000
160
10
nA
µA
pF
I
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
CC
C
2 V to 6 V
3
10
10
i
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC163
SN74HC163
A
V
UNIT
CC
MIN
MAX
6
MIN
MAX
4.2
21
MIN
MAX
5
2 V
4.5 V
6 V
31
25
f
t
Clock frequency
Pulse duration
MHz
clock
36
25
29
2 V
80
16
14
150
30
26
135
27
23
170
34
29
160
32
27
160
32
27
0
120
24
20
225
45
38
205
41
35
255
51
43
240
48
41
240
48
41
0
100
20
17
190
38
32
170
34
29
215
43
37
200
40
34
200
40
34
0
4.5 V
6 V
CLK high or low
A, B, C, or D
LOAD low
ns
ns
ns
w
2 V
4.5 V
6 V
2 V
4.5 V
6 V
2 V
4.5 V
6 V
t
su
Setup time before CLK↑
ENP, ENT
2 V
4.5 V
6 V
CLR low
2 V
4.5 V
6 V
CLR inactive
2 V
t
h
Hold time, all synchronous inputs after CLK↑
4.5 V
6 V
0
0
0
0
0
0
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢊ ꢃ ꢄꢅꢆ ꢇ ꢈ
ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢅ ꢄ ꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁ ꢓꢐꢏ ꢅꢑ ꢒꢁ ꢎꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
14
40
44
83
24
20
80
25
21
62
17
14
38
8
SN54HC163
SN74HC163
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
MAX
MIN
4.2
21
MAX
MIN
5
MAX
2 V
4.5 V
6 V
31
36
25
29
f
t
t
MHz
max
pd
t
25
2 V
215
43
325
65
270
54
4.5 V
6 V
RCO
Any Q
RCO
Any
37
55
46
CLK
ENT
2 V
205
41
310
62
255
51
4.5 V
6 V
ns
ns
35
53
43
2 V
195
39
295
59
245
49
4.5 V
6 V
33
50
42
2 V
75
110
22
95
4.5 V
6 V
15
19
6
13
19
16
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
60
pF
pd
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
50%
50%
50%
Pulse
From Output
Under Test
Test
Point
0 V
t
w
C
= 50 pF
L
V
CC
Low-Level
Pulse
(see Note A)
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢊ ꢃ ꢄꢅꢆ ꢇ ꢈ
ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢅ ꢄ ꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁ ꢓꢐꢏ ꢅꢑ ꢒꢁ ꢎꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
APPLICATION INFORMATION
n-bit synchronous counters
This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit
counter. The ’HC163 devices count in binary. Virtually any count mode (modulo-N, N -to-N , N -to-maximum)
1
2
1
can be used with this fast look-ahead circuit.
The application circuit shown in Figure 2 is not valid for clock frequencies above 18 MHz (at 25°C and
4.5-V V ). The reason for this is that there is a glitch that is produced on the second stage’s RCO and every
CC
succeeding stage’s RCO. This glitch is common to all HC vendors that Texas Instruments has evaluated, in
addition to the bipolar equivalents (LS, ALS, AS).
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
APPLICATION INFORMATION
LSB
CTR
CLR
Clear (L)
CT=0
LOAD
M1
RCO
RCO
RCO
RCO
3CT=MAX
ENT
Count (H)/
Disable (L)
G3
ENP
G4
CLK
C5/2,3,4+
Load (L)
[1]
[2]
[3]
[4]
A
B
C
D
1,5D
Q
Q
Q
Q
A
B
C
D
Count (H)/
Disable (L)
Clock
CTR
CLR
LOAD
ENT
CT=0
M1
3CT=MAX
G3
ENP
CLK
G4
C5/2,3,4+
[1]
[2]
[3]
[4]
A
B
C
D
1,5D
Q
Q
Q
Q
A
B
C
D
CTR
CLR
LOAD
ENT
CT=0
M1
3CT=MAX
G3
ENP
CLK
G4
C5/2,3,4+
[1]
[2]
[3]
[4]
A
B
C
D
1,5D
Q
Q
Q
Q
A
B
C
D
CTR
CLR
CT=0
M1
LOAD
ENT
3CT=MAX
G3
ENP
CLK
G4
C5/2,3,4+
A
B
C
D
1,5D [1]
Q
Q
Q
Q
A
B
C
D
[2]
[3]
[4]
To More-Significant Stages
Figure 2
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢊ ꢃ ꢄꢅꢆ ꢇ ꢈ
ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢅ ꢄ ꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁ ꢓꢐꢏ ꢅꢑ ꢒꢁ ꢎꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
APPLICATION INFORMATION
n-bit synchronous counters (continued)
The glitch on RCO is caused because the propagation delay of the rising edge of Q of the second stage is
A
shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, Q , Q , Q , and Q
A
B
C
D
(ENT × Q × Q × Q × Q ). The resulting glitch is about 7−12 ns in duration. Figure 3 shows the condition in
A
B
C
D
which the glitch occurs. For simplicity, only two stages are being considered, but the results can be applied to
other stages. Q , Q , and Q of the first and second stage are at logic one, and Q of both stages are at logic
B
C
D
A
zero (1110 1110) after the first clock pulse. On the rising edge of the second clock pulse, Q and RCO of the
A
first stage go high. On the rising edge of the third clock pulse, Q and RCO of the first stage return to a low level,
A
and Q of the second stage goes to a high level. At this time, the glitch on RCO of the second stage appears
A
because of the race condition inside the chip.
1
2
3
4
5
CLK
ENT1
Q
, Q , Q
B1 C1 D1
Q
A1
RCO1, ENT2
Q
, Q , Q
B2 C2 D2
Q
A2
RCO2
Glitch (7−12 ns)
Figure 3
The glitch causes a problem in the next stage (stage three) if the glitch is still present when the next rising clock
edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than the
inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (t ). In other words,
g
f
= 1/(t CLK-to-RCO + t ). For example, at 25°C at 4.5-V V , the clock-to-RCO propagation delay is
max
pd g CC
43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the
cascaded counters can use is 18 MHz. The following tables contain the f
applications that use more than two ’HC163 devices cascaded together.
, t , and f
specifications for
clock
w
max
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢅꢄꢐꢑ ꢁꢑ ꢒꢀ ꢌꢍ ꢁꢓꢐꢏ ꢅꢑ ꢒ ꢁꢎ ꢔꢐ ꢀ
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003
APPLICATION INFORMATION
n-bit synchronous counters (continued)
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC163
SN74HC163
A
V
UNIT
CC
MIN
MAX
3.6
18
MIN
MAX
2.5
12
MIN
MAX
2.9
14
2 V
4.5 V
6 V
f
t
Clock frequency
MHz
clock
21
14
17
2 V
140
28
200
40
170
36
Pulse duration, CLK high or low
4.5 V
6 V
ns
w
24
36
30
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Note 4)
T = 25°C
A
SN54HC163
SN74HC163
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
3.6
18
MAX
MIN
2.5
12
MAX
MIN
2.9
14
MAX
2 V
4.5 V
6 V
f
MHz
max
21
14
17
NOTE 4: These limits apply only to applications that use more than two ’HC163 devices cascaded together.
If the ’HC163 devices are used as a single unit, or only two cascaded together, then the maximum clock
frequency that the devices can use is not limited because of the glitch. In these situations, the devices can be
operated at the maximum specifications.
A glitch can appear on RCO of a single ’HC163 device, depending on the relationship of ENT to CLK. Any
application that uses RCO to drive any input, except an ENT of another cascaded ’HC163 device, must take
this into consideration.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
86076012A
8607601EA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
16
16
16
16
16
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42
A42
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
8607601FA
W
J
JM38510/66304BEA
SN54HC163J
SN74HC163D
CDIP
CDIP
SOIC
J
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC163DBR
SN74HC163DBRE4
SN74HC163DBRG4
SN74HC163DE4
SN74HC163DG4
SN74HC163DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
DB
DB
DB
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC163DRE4
SN74HC163DRG4
SN74HC163DT
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC163DTE4
SN74HC163DTG4
SN74HC163N
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74HC163NE4
SN74HC163NSR
SN74HC163NSRE4
SN74HC163NSRG4
SN74HC163PW
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SO
NS
NS
NS
PW
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC163PWE4
SN74HC163PWG4
SN74HC163PWR
SN74HC163PWRE4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74HC163PWRG4
SN74HC163PWT
TSSOP
PW
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
PW
PW
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC163PWTE4
SN74HC163PWTG4
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54HC163FK
SNJ54HC163J
SNJ54HC163W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
16
16
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC163, SN74HC163 :
Automotive: SN74HC163-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74HC163DBR
SN74HC163DR
SN74HC163NSR
SN74HC163PWR
SSOP
SOIC
SO
DB
D
16
16
16
16
2000
2500
2000
2000
330.0
330.0
330.0
330.0
16.4
16.4
16.4
12.4
8.2
6.5
8.2
7.0
6.6
10.3
10.5
5.6
2.5
2.1
2.5
1.6
12.0
8.0
16.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
NS
PW
12.0
8.0
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HC163DBR
SN74HC163DR
SN74HC163NSR
SN74HC163PWR
SSOP
SOIC
SO
DB
D
16
16
16
16
2000
2500
2000
2000
346.0
333.2
346.0
346.0
346.0
345.9
346.0
346.0
33.0
28.6
33.0
29.0
NS
PW
TSSOP
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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