概述
规格参数
数据手册
替代型号SN74HC164PWG4 概述
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS 8位并行输出串行移位寄存器 移位寄存器
SN74HC164PWG4 规格参数
| 是否Rohs认证： | 符合 | 生命周期： | Obsolete |
| 零件包装代码： | TSSOP | 包装说明： | TSSOP-14 |
| 针数： | 14 | Reach Compliance Code： | compliant |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.04 |
| Is Samacsys： | N | 计数方向： | RIGHT |
| 系列： | HC/UH | JESD-30 代码： | R-PDSO-G14 |
| JESD-609代码： | e4 | 长度： | 5 mm |
| 逻辑集成电路类型： | SERIAL IN PARALLEL OUT | 最大频率@ Nom-Sup： | 5000000 Hz |
| 湿度敏感等级： | 1 | 位数： | 8 |
| 功能数量： | 1 | 端子数量： | 14 |
| 最高工作温度： | 125 °C | 最低工作温度： | -40 °C |
| 输出极性： | TRUE | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | TSSOP | 封装等效代码： | TSSOP14,.25 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
| 峰值回流温度（摄氏度）： | 260 | 电源： | 2/6 V |
| 传播延迟（tpd）： | 220 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 1.2 mm | 子类别： | Shift Registers |
| 最大供电电压 (Vsup)： | 6 V | 最小供电电压 (Vsup)： | 2 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | AUTOMOTIVE |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | GULL WING |
| 端子节距： | 0.65 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 触发器类型： | POSITIVE EDGE |
| 宽度： | 4.4 mm | 最小 fmax： | 28 MHz |
| Base Number Matches： | 1 |
SN74HC164PWG4 数据手册
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PDF下载ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢃ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢃ
ꢊ ꢋꢌꢍ ꢎ ꢏꢐꢑꢐ ꢒꢒ ꢓꢒ ꢋꢔ ꢕꢎ ꢀꢓ ꢑꢍꢐ ꢒ ꢀꢄ ꢍꢖ ꢎ ꢑꢓ ꢗ ꢍꢀ ꢎꢓ ꢑ ꢀ
SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
SN54HC164 . . . J OR W PACKAGE
SN74HC164 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
Typical t = 20 ns
pd
4-mA Output Drive at 5 V
A
B
V
CC
Q
Q
Q
Q
H
G
F
Q
A
B
C
D
Low Input Current of 1 µA Max
AND-Gated (Enable/Disable) Serial Inputs
Fully Buffered Clock and Serial Inputs
Direct Clear
Q
Q
Q
E
CLR
CLK
8
GND
description/ordering information
SN54HC164 . . . FK PACKAGE
(TOP VIEW)
These 8-bit shift registers feature AND-gated
serial inputs and an asynchronous clear (CLR)
input. The gated serial (A and B) inputs permit
complete control over incoming data; a low at
either input inhibits entry of the new data and
resets the first flip-flop to the low level at the next
clock (CLK) pulse. A high-level input enables the
other input, which then determines the state of the
first flip-flop. Data at the serial inputs can be
changed while CLK is high or low, provided the
minimum setup time requirements are met.
Clocking occurs on the low-to-high-level transition
of CLK.
3
2
1
20 19
18
Q
Q
4
5
6
7
8
G
A
NC
NC
17
16
Q
F
Q
B
NC
15 NC
14
9 10 11 12 13
Q
Q
C
E
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 25
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HC164N
SN74HC164N
SN74HC164D
SN74HC164DR
SN74HC164DT
SN74HC164NSR
SN74HC164PW
SN74HC164PWR
SN74HC164PWT
SNJ54HC164J
SNJ54HC164W
SNJ54HC164FK
SOIC − D
SOP − NS
HC164
HC164
−40°C to 85°C
TSSOP − PW
HC164
CDIP − J
CFP − W
LCCC − FK
SNJ54HC164J
SNJ54HC164W
SNJ54HC164FK
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
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ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑ ꢐꢒ ꢒ ꢓ ꢒꢋꢔ ꢕꢎ ꢀ ꢓꢑ ꢍ ꢐꢒ ꢀ ꢄꢍ ꢖꢎ ꢑ ꢓꢗ ꢍꢀ ꢎꢓ ꢑꢀ
SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
FUNCTION TABLE
INPUTS
CLK
OUTPUTS
. . . Q
CLR
L
A
B
X
X
H
X
L
Q
Q
B
A
H
X
L
↑
↑
↑
X
X
H
L
L
L
L
H
Q
Q
Q
H0
Q
Gn
Q
Gn
Q
Gn
A0
B0
An
An
An
H
H
L
L
Q
Q
Q
H
H
X
Q
, Q , Q = the level of Q , Q , or Q , respectively,
A0 B0 H0 A B H
before the indicated steady-state input conditions were
established
Q
, Q = the level of Q or Q before the most recent
An Gn A G
↑ transition of CLK: indicates a 1-bit shift
logic diagram (positive logic)
8
CLK
1
2
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
A
B
R
R
R
R
R
R
R
R
9
CLR
3
4
5
6
10
11
12
13
Q
Q
Q
Q
Q
Q
Q
Q
H
A
B
C
D
E
F
G
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
2
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ꢊ ꢋꢌꢍ ꢎ ꢏꢐꢑꢐ ꢒꢒ ꢓꢒ ꢋꢔ ꢕꢎ ꢀꢓ ꢑꢍꢐ ꢒ ꢀꢄ ꢍꢖ ꢎ ꢑꢓ ꢗ ꢍꢀ ꢎꢓ ꢑ ꢀ
SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
typical clear, shift, and clear sequence
CLR
A
B
CLK
Q
Q
Q
Q
A
B
C
D
Q
E
Q
F
Q
G
Q
H
Clear
Clear
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3
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SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HC164
MIN NOM
SN74HC164
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
†
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
−55
−40
°C
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
†
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
IL
IH
= 2 V does not damage the device; however, functionally,
t
CC
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC164
SN74HC164
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
V
V
V = V or V
IH
V
OH
OL
I
IL
I
I
= −4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= −5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
8
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
V = V or V
V
I
IH
IL
I
I
= 4 mA
4.5 V
6 V
0.4
0.33
0.33
1000
80
OL
= 5.2 mA
0.4
OL
I
I
V = V
I
or 0
6 V
1000
160
10
nA
µA
pF
I
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
CC
C
2 V to 6 V
3
10
10
i
4
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SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC164
SN74HC164
A
V
UNIT
CC
MIN
MAX
6
MIN
MAX
4.2
21
MIN
MAX
5
2 V
4.5 V
6 V
31
25
f
Clock frequency
Pulse duration
MHz
clock
36
25
28
2 V
100
20
17
80
16
14
100
20
17
100
20
17
5
150
30
25
120
24
20
150
30
25
150
30
25
5
125
25
21
100
20
18
125
25
21
125
25
21
5
4.5 V
6 V
CLR low
t
w
ns
2 V
4.5 V
6 V
CLK high or low
Data
2 V
4.5 V
6 V
t
t
Setup time before CLK↑
ns
ns
su
2 V
4.5 V
6 V
CLR inactive
2 V
Hold time, data after CLK↑
4.5 V
6 V
5
5
5
h
5
5
5
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
10
SN54HC164
SN74HC164
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
MAX
MIN
4.2
21
MAX
MIN
5
MAX
2 V
4.5 V
6 V
31
36
54
25
28
f
t
t
t
MHz
max
PHL
pd
62
25
2 V
140
28
205
41
295
59
255
51
4.5 V
6 V
CLR
CLK
Any Q
Any Q
24
35
51
46
ns
ns
2 V
115
23
175
35
265
53
220
44
4.5 V
6 V
20
30
45
38
2 V
38
75
110
22
95
4.5 V
6 V
8
15
19
t
6
13
19
16
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
135
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
50%
50%
50%
Pulse
From Output
Under Test
Test
Point
0 V
t
w
C
= 50 pF
L
V
CC
Low-Level
Pulse
(see Note A)
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CFP
Drawing
5962-8416201VCA
5962-8416201VDA
84162012A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
W
FK
J
14
14
20
14
14
14
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
LCCC
CDIP
CDIP
SOIC
POST-PLATE N / A for Pkg Type
8416201CA
A42
A42
N / A for Pkg Type
N / A for Pkg Type
SN54HC164J
SN74HC164D
J
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC164DE4
SN74HC164DG4
SN74HC164DR
SN74HC164DRE4
SN74HC164DRG4
SN74HC164DT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
D
D
D
D
D
D
N
14
14
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC164DTE4
SN74HC164DTG4
SN74HC164N
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74HC164N3
SN74HC164NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
14
14
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74HC164NSR
SN74HC164NSRE4
SN74HC164NSRG4
SN74HC164PW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
14
14
14
14
14
14
14
14
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC164PWE4
SN74HC164PWG4
SN74HC164PWR
SN74HC164PWRE4
SN74HC164PWRG4
SN74HC164PWT
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
Orderable Device
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74HC164PWTE4
SN74HC164PWTG4
TSSOP
PW
14
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
PW
14
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54HC164FK
SNJ54HC164J
SNJ54HC164W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC164DR
SN74HC164DR
SN74HC164DR
SN74HC164DT
SN74HC164NSR
SN74HC164PWR
SN74HC164PWT
SOIC
SOIC
SOIC
SOIC
SO
D
D
14
14
14
14
14
14
14
2500
2500
2500
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
12.4
12.4
6.5
6.55
6.5
6.5
8.2
6.9
6.9
9.0
9.05
9.0
2.1
2.1
2.1
2.1
2.5
1.6
1.6
8.0
8.0
8.0
8.0
12.0
8.0
8.0
16.0
16.0
16.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
D
D
9.0
NS
PW
PW
2000
2000
250
10.5
5.6
TSSOP
TSSOP
5.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HC164DR
SN74HC164DR
SN74HC164DR
SN74HC164DT
SN74HC164NSR
SN74HC164PWR
SN74HC164PWT
SOIC
SOIC
SOIC
SOIC
SO
D
D
14
14
14
14
14
14
14
2500
2500
2500
250
333.2
385.0
346.0
346.0
346.0
346.0
346.0
345.9
388.0
346.0
346.0
346.0
346.0
346.0
28.6
194.0
33.0
33.0
33.0
29.0
29.0
D
D
NS
PW
PW
2000
2000
250
TSSOP
TSSOP
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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SN74HC164PWG4 CAD模型
引脚图
封装焊盘图
SN74HC164PWG4 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| SN74HC164PWR | TI | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS | 完全替代 |
|
| SN74HC164PWT | TI | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS | 完全替代 |
|
| SN74HC164PWRG4 | TI | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS | 完全替代 |
|
SN74HC164PWG4 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| SN74HC164PWR | TI | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS | 获取价格 |
|
| SN74HC164PWRE4 | TI | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS | 获取价格 |
|
| SN74HC164PWRG4 | TI | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS | 获取价格 |
|
| SN74HC164PWT | TI | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS | 获取价格 |
|
| SN74HC164PWTE4 | TI | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS | 获取价格 |
|
| SN74HC164PWTG4 | TI | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS | 获取价格 |
|
| SN74HC164_09 | TI | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS | 获取价格 |
|
| SN74HC165 | TI | 8-BIT PARALLEL-LOAD SHIFT REGISTERS | 获取价格 |
|
| SN74HC165-EP | TI | 8-BIT PARALLEL-LOAD SHIFT REGISTER | 获取价格 |
|
| SN74HC165-Q1 | TI | 8-BIT PARALLEL-LOAD SHIFT REGISTER | 获取价格 |
|
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