SN74HC165QPWRG4Q1 [TI]
汽车类 8 位并联负载移位寄存器 | PW | 16 | -40 to 125;
| 型号： | SN74HC165QPWRG4Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 8 位并联负载移位寄存器 | PW | 16 | -40 to 125 PC 光电二极管 逻辑集成电路 触发器 移位寄存器 |
| 文件： | 总11页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢋ ꢉꢌꢍ ꢎ ꢏꢐꢑꢐ ꢒꢒ ꢓꢒ ꢉꢒ ꢔ ꢐꢕ ꢀꢄꢍ ꢖ ꢎ ꢑꢓ ꢗ ꢍꢀ ꢎꢓ ꢑ
SCLS518 − AUGUST 2003
D OR PW PACKAGE
(TOP VIEW)
D
Qualification in Accordance With
AEC-Q100
†
D
Qualified for Automotive Applications
1
2
3
4
5
6
7
8
SH/LD
CLK
E
16
V
CC
D
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
15 CLK INH
14
13
12
11
D
C
B
A
F
G
H
D
ESD Protection Exceeds 1500 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Q
10 SER
H
GND
9
Q
H
D
D
D
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I
Typical t = 13 ns
pd
4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Complementary Outputs
CC
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
Parallel-to-Serial Data Conversion
†
Contact factory for details. Q100 qualification data available on
request.
description/ordering information
The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (Q )
H
output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled
by a low level at the shift/load (SH/LD) input. The SN74HC165 also features a clock-inhibit (CLK INH) function
and a complementary serial (Q ) output.
H
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK
INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high
transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK
is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the
register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
SOIC − D
Tape and reel
Tape and reel
SN74HC165QDRQ1
SN74HC165QPWRQ1
HC165Q1
HC165Q1
−40°C to 125°C
TSSOP − PW
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
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SCLS518 − AUGUST 2003
FUNCTION TABLE
INPUTS
FUNCTION
SH/LD
CLK CLK INH
L
X
H
X
L
X
X
H
↑
L
Parallel load
No change
No change
H
H
H
H
†
Shift
†
Shift
↑
†
Shift = content of each internal register shifts
toward serial output Q . Data at SER is
H
shifted into the first register.
logic diagram (positive logic)
A
B
C
D
E
F
G
H
11
12
13
14
3
4
5
6
1
SH/LD
9
15
2
Q
H
CLK INH
CLK
S
C1
S
C1
S
C1
S
C1
S
C1
S
C1
S
C1
S
C1
10
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
SER
7
Q
H
2
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SCLS518 − AUGUST 2003
typical shift, load, and inhibit sequence
CLK
CLK INH
SER
L
SH/LD
A
H
L
B
C
H
Data
Inputs
L
D
E
H
F
L
H
H
G
H
H
L
H
L
L
H
L
L
H
L
L
H
L
Q
Q
H
H
H
H
H
Inhibit
Serial Shift
Load
3
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SCLS518 − AUGUST 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM
MAX
UNIT
V
Supply voltage
2
1.5
5
6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
V
High-level input voltage
V
V
= 2 V
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
‡
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
−40
°C
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
‡
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
IL
IH
= 2 V does not damage the device; however, functionally,
t
CC
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
4
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SCLS518 − AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
CC
MIN
MAX
UNIT
MIN
TYP
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
1.9
4.4
5.9
3.7
5.2
I
= −20 µA
OH
V
V
V = V or V
IH
V
OH
OL
I
IL
I
I
= −4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
OH
= −5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
8
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
V = V or V
V
I
IH
IL
I
I
= 4 mA
4.5 V
6 V
0.4
OL
= 5.2 mA
0.4
OL
I
I
V = V
or 0
6 V
1000
160
10
nA
µA
pF
I
I
CC
V = V
or 0,
I
O
= 0
6 V
CC
I
CC
C
2 V to 6 V
3
10
i
5
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SCLS518 − AUGUST 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
A
V
MIN
MAX
UNIT
CC
MIN
MAX
6
2 V
4.5 V
6 V
4.2
21
25
31
f
Clock frequency
Pulse duration
MHz
clock
36
2 V
80
16
14
80
16
14
80
16
14
40
8
120
24
20
120
24
20
120
24
20
60
12
10
150
30
25
60
12
10
150
30
26
5
4.5 V
6 V
SH/LD low
t
w
ns
ns
ns
2 V
4.5 V
6 V
CLK high or low
2 V
4.5 V
6 V
SH/LD high before CLK↑
SER before CLK↑
2 V
4.5 V
6 V
7
2 V
100
20
17
40
8
4.5 V
6 V
t
su
Setup time
CLK INH low before CLK↑
CLK INH high before CLK↑
Data before SH/LD↓
SER data after CLK↑
PAR data after SH/LD↓
2 V
4.5 V
6 V
7
2 V
100
20
17
5
4.5 V
6 V
2 V
4.5 V
6 V
5
5
5
5
t
h
Hold time
2 V
5
5
4.5 V
6 V
5
5
5
5
6
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SCLS518 − AUGUST 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
13
50
62
80
20
16
75
15
13
75
15
13
38
8
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
MIN
MAX
UNIT
CC
MIN
6
MAX
2 V
4.5 V
6 V
4.2
21
25
31
36
f
t
t
MHz
max
pd
t
2 V
150
30
225
45
4.5 V
6 V
SH/LD
CLK
H
Q
Q
Q
or Q
or Q
or Q
H
H
H
H
H
H
26
38
2 V
150
30
225
45
4.5 V
6 V
ns
ns
26
38
2 V
150
30
225
45
4.5 V
6 V
26
38
2 V
75
110
22
Any
4.5 V
6 V
15
6
13
19
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
75
pF
pd
7
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SCLS518 − AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
50%
50%
50%
Pulse
From Output
Under Test
Test
Point
0 V
t
w
C
= 50 pF
L
V
CC
Low-Level
Pulse
(see Note A)
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN74HC166D-00
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