SN74HC259PWR_技术文档

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SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003

SN54HC259 . . . J OR W PACKAGE

SN74HC259 . . . D, N, NS, OR PW PACKAGE

(TOP VIEW)

D

Wide Operating Voltage Range of 2 V to 6 V

High-Current Inverting Outputs Drive Up To

10 LSTTL Loads

D

Low Power Consumption, 80-µA Max I

Typical t = 14 ns

pd

4-mA Output Drive at 5 V

CC

S0

S1

S2

Q0

Q1

Q2

Q3

GND

1

2

3

4

5

6

7

8

16

V

CC

15 CLR

14

13

12

11

10

9

G

D

Q7

Q6

Q5

Q4

Low Input Current of 1 µA Max

8-Bit Parallel-Out Storage Register

Performs Serial-to-Parallel Conversion With

Storage

D

Asynchronous Parallel Clear

Active-High Decoder

SN54HC259 . . . FK PACKAGE

(TOP VIEW)

Enable Input Simplifies Expansion

Expandable for n-Bit Applications

Four Distinct Functional Modes

3

2

1

20 19

18

S2

Q0

NC

Q1

Q2

G

4

5

6

7

8

description/ordering information

17

16

15

14

D

NC

Q7

Q6

These 8-bit addressable latches are designed for

general-purpose storage applications in digital

systems. Specific uses include working registers,

serial-holding registers, and active-high decoders

or demultiplexers. They are multifunctional

devices capable of storing single-line data in eight

addressable latches and being a 1-of-8 decoder

or demultiplexer with active-high outputs.

9 10 11 12 13

NC − No internal connection

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

PDIP − N

SOIC − D

Tube of 25

Tube of 40

Reel of 2500

Reel of 250

Reel of 2000

Reel of 250

Tube of 25

Tube of 150

Tube of 55

SN74HC259N

SN74HC259D

SN74HC259DR

SN74HC259DT

SN74HC259NSR

SN74HC259PWR

SN74HC259PWT

SNJ54HC259J

SNJ54HC259W

SNJ54HC259FK

HC259

−40°C to 85°C

SOP − NS

HC259

TSSOP − PW

CDIP − J

CFP − W

LCCC − FK

SNJ54HC259J

SNJ54HC259W

SNJ54HC259FK

−55°C to 125°C

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2003, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊꢋ ꢌꢍ ꢎ ꢏ ꢐ ꢐꢑ ꢒꢀ ꢀꢏ ꢌꢓ ꢒ ꢓꢏꢎꢅ ꢄꢒ ꢀ

SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003

description/ordering information (continued)

Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In the

addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch

follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode, all

latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the

possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines

are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the

D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data

inputs.

Function Tables

FUNCTION

OUTPUT OF

ADDRESSED

LATCH

EACH

OTHER

OUTPUT

INPUTS

FUNCTION

CLR

G

L

H

L

D

Q

Addressable latch

Memory

iO

H

L

Q

iO

D

L

8-line demultiplexer

Clear

L

H

L

LATCH SELECTION

SELECT INPUTS

LATCH

ADDRESSED

S2

S1

L

S0

L

H

L

0

1

2

3

4

5

6

7

L

H

L

H

L

H

L

H

L

H

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003

logic diagram

D

4

1

S0

C

R

Q

Q0

Q1

Q2

Q3

Q4

Q5

D

C

5

6

R

D

C

2

3

S1

S2

R

D

C

7

R

D

C

9

R

D

C

10

R

14

13

15

G

D

C

11

12

Q

Q6

Q7

R

D

C

R

CLR

Pin numbers shown are for the D, J, N, NS, PW, and W packages.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003

logic diagram, each internal latch (positive logic)

C

D

C

TG

C

Q

C

TG

C

R

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

I

Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

IK

I

CC

Output clamp current, I

(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

OK

O O CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA

Continuous current through V

O

CC

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W

JA

N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54HC259

MIN NOM

SN74HC259

MIN NOM

UNIT

MAX

V

Supply voltage

2

1.5

5

6

2

1.5

5

6

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2 V

= 4.5 V

= 6 V

3.15

4.2

3.15

4.2

High-level input voltage

V

IH

= 2 V

0.5

1.35

1.8

0.5

1.35

1.8

= 4.5 V

= 6 V

V

IL

Low-level input voltage

V

Input voltage

0

V

0

V

I

CC

Output voltage

O

CC

V

CC

V

CC

V

CC

= 2 V

1000

500

400

125

1000

500

400

85

= 4.5 V

= 6 V

∆t/∆v

Input transition rise/fall time

ns

T

A

Operating free-air temperature

−55

−40

°C

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

T

= 25°C

SN54HC259

SN74HC259

A

PARAMETER

TEST CONDITIONS

V

UNIT

CC

MIN

TYP

MAX

MIN

1.9

4.4

5.9

3.7

5.2

MAX

MIN

1.9

MAX

2 V

4.5 V

6 V

1.9 1.998

4.4 4.499

5.9 5.999

4.4

I

= −20 µA

OH

5.9

V

V = V or V

IH

V

OH

OL

I

IL

I

= −4 mA

4.5 V

6 V

3.98

5.48

4.3

5.8

3.84

5.34

OH

= −5.2 mA

OH

2 V

0.002

0.001

0.17

0.15

0.1

0.26

100

8

0.1

4.5 V

6 V

I

= 20 µA

OL

0.1

V = V or V

V

I

IH

IL

I

= 4 mA

4.5 V

6 V

0.4

0.33

1000

80

OL

= 5.2 mA

0.4

OL

I

V = V

I

or 0

6 V

1000

160

10

nA

µA

pF

I

CC

V = V

I

or 0,

I

O

= 0

6 V

CC

C

2 V to 6 V

3

10

i

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

T

= 25°C

SN54HC259

SN74HC259

A

V

UNIT

CC

MIN

80

16

14

80

16

14

75

15

13

5

MAX

MIN

120

24

20

120

24

20

115

23

20

5

MAX

MIN

100

20

17

100

20

17

95

19

16

5

MAX

2 V

4.5 V

6 V

CLR low

G low

t

w

Pulse duration

ns

2 V

4.5 V

6 V

2 V

4.5 V

6 V

t

Setup time, data or address before G↑

Hold time, data or address after G↑

ns

su

2 V

4.5 V

6 V

5

h

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003

switching characteristics over recommended operating free-air temperature range, C = 50 pF

L

(unless otherwise noted) (see Figure 1)

T

A

= 25°C

TYP

60

18

14

56

17

13

74

21

17

66

20

16

28

8

SN54HC259

SN74HC259

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

V

UNIT

CC

MIN

MAX

150

30

MIN

MAX

225

45

MIN

MAX

190

38

2 V

4.5 V

6 V

t

CLR

Data

Any Q

Any

ns

PHL

pd

t

26

38

32

2 V

130

26

195

39

165

33

4.5 V

6 V

22

33

28

2 V

200

40

300

60

250

50

4.5 V

6 V

Address

G

ns

34

51

43

2 V

170

34

255

51

215

43

4.5 V

6 V

29

43

37

2 V

75

110

22

95

4.5 V

6 V

15

19

6

13

19

16

operating characteristics, T = 25°C

A

PARAMETER

TEST CONDITIONS

TYP

UNIT

C

Power dissipation capacitance per latch

No load

33

pF

pd

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003

PARAMETER MEASUREMENT INFORMATION

V

CC

High-Level

Pulse

50%

From Output

Under Test

Test

Point

0 V

t

w

C

= 50 pF

L

V

CC

(see Note A)

Low-Level

Pulse

50%

0 V

LOAD CIRCUIT

VOLTAGE WAVEFORMS

PULSE DURATIONS

V

CC

Input

50%

0 V

V

t

PLH

PHL

90%

V

CC

OH

In-Phase

Output

Reference

Input

90%

t

50%

10%

50%

10%

V

OL

0 V

V

t

r

f

t

h

su

t

PLH

PHL

90%

V

CC

OH

OL

Data

Input

90%

t

Out-of-Phase

Output

50%

10%

50%

10%

50%

10%

50%

10%

0 V

V

t

r

f

VOLTAGE WAVEFORMS

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

NOTES: A.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.

C includes probe and test-fixture capacitance.

L

O

r

f

C. The outputs are measured one at a time with one input transition per measurement.

D. and t are the same as t

t

.

PLH

PHL pd

Figure 1. Load Circuit and Voltage Waveforms

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MCFP004A– JANUARY 1995 – REVISED FEBRUARY 2002

W (R-GDFP-F16)

CERAMIC DUAL FLATPACK

Base and Seating Plane

0.285 (7,24)

0.245 (6,22)

0.045 (1,14)

0.026 (0,66)

0.006 (0,15)

0.004 (0,10)

0.080 (2,03)

0.055 (1,40)

0.305 (7,75) MAX

0.019 (0,48)

0.015 (0,38)

1

16

0.050 (1,27)

0.430 (10,92)

0.370 (9,40)

0.005 (0,13) MIN

4 Places

8

9

0.360 (9,14)

0.250 (6,35)

0.360 (9,14)

0.250 (6,35)

4040180-3/C 02/02

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification only.

E. Falls within MIL STD 1835 GDFP-1F16 and JEDEC MO-092AC

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL

MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002

N (R-PDIP-T**)

PLASTIC DUAL-IN-LINE PACKAGE

16 PINS SHOWN

PINS **

14

16

18

20

DIM

0.775

0.920

1.060

A MAX

A

(19,69) (19,69) (23,37) (26,92)

16

9

0.745

0.850

0.940

A MIN

(18,92) (18,92) (21,59) (23,88)

MS-100

VARIATION

0.260 (6,60)

0.240 (6,10)

AA

BB

AC

AD

C

1

8

0.070 (1,78)

0.045 (1,14)

D

0.045 (1,14)

0.325 (8,26)

0.300 (7,62)

0.020 (0,51) MIN

D

0.030 (0,76)

0.015 (0,38)

Gauge Plane

0.200 (5,08) MAX

Seating Plane

0.010 (0,25) NOM

0.125 (3,18) MIN

0.100 (2,54)

0.430 (10,92) MAX

0.021 (0,53)

0.015 (0,38)

0.010 (0,25)

M

14/18 PIN ONLY

20 pin vendor option

D

4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).

D. The 20 pin end lead shoulder width is a vendor option, either half or full width.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

8 PINS SHOWN

0.020 (0,51)

0.014 (0,35)

0.050 (1,27)

8

0.010 (0,25)

5

0.244 (6,20)

0.228 (5,80)

0.008 (0,20) NOM

0.157 (4,00)

0.150 (3,81)

Gage Plane

1

4

0.010 (0,25)

0°– 8°

A

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

0.069 (1,75) MAX

0.004 (0,10)

PINS **

8

14

16

DIM

A MAX

0.197

(5,00)

0.344

(8,75)

0.394

(10,00)

0.189

(4,80)

0.337

(8,55)

0.386

(9,80)

A MIN

4040047/E 09/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-012

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

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Amplifiers

amplifier.ti.com

www.ti.com/audio

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dataconverter.ti.com

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www.ti.com/automotive

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dsp.ti.com

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Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

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Logic

interface.ti.com

logic.ti.com

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Microcontrollers

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Security

www.ti.com/opticalnetwork

www.ti.com/security

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www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

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Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	SN74HC259PWR
厂家：	TEXAS INSTRUMENTS
描述：	8-BIT ADDRESSABLE LATCHES 8位可寻址锁存器触发器锁存器逻辑集成电路光电二极管双倍数据速率
文件：	总15页 (文件大小：365K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74HC259PWR [TI]

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