SN74HC4040N-00 [TI]
HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDIP16;
| 型号： | SN74HC4040N-00 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDIP16 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总23页 (文件大小：1219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢃ ꢆꢃ ꢆ ꢇ ꢀꢁ ꢈꢃ ꢄꢅ ꢃꢆ ꢃꢆ
ꢉ ꢊ ꢋꢌꢍ ꢎ ꢏꢀ ꢐꢁꢅꢄꢑ ꢒꢁ ꢒꢓ ꢀ ꢌꢍ ꢁꢏꢑꢐ ꢅꢒ ꢓ ꢁꢎ ꢔꢑ ꢀ
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
D
D
D
Typical t = 12 ns
pd
4-mA Output Drive at 5 V
Low Power Consumption, 80-µA Max I
Low Input Current of 1 µA Max
CC
SN54HC4040 . . . FK PACKAGE
(TOP VIEW)
SN54HC4040 . . . J OR W PACKAGE
SN74HC4040 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L
3
2
1
20 19
18
Q
Q
Q
Q
F
E
K
J
H
I
Q
Q
Q
Q
4
5
6
7
8
J
E
Q
Q
17
16
15
14
H
G
G
NC
NC
Q
D
C
Q
I
CLR
Q
D
Q
CLR
CLK
Q
C
Q
9 10 11 12 13
B
GND
Q
A
NC − No internal connection
description/ordering information
The ’HC4040 devices are 12-stage asynchronous binary counters, with the outputs of all stages available
externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low.
The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay
circuits, counter controls, and frequency-dividing circuits.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
†
T
A
PACKAGE
PDIP − N
PACKAGE
Tube of 25
Tube of 40
SN74HC4040N
SN74HC4040N
SN74HC4040D
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
SN74HC4040DR
SN74HC4040DT
SN74HC4040NSR
SN74HC4040DBR
SN74HC4040PW
SN74HC4040PWR
SN74HC4040PWT
SNJ54HC4040J
SNJ54HC4040W
SNJ54HC4040FK
SOIC − D
HC4040
SOP − NS
HC4040
HC4040
−40°C to 85°C
SSOP − DB
Reel of 2000
Reel of 250
Tube of 25
TSSOP − PW
HC4040
CDIP − J
CFP − W
LCCC − FK
SNJ54HC4040J
SNJ54HC4040W
SNJ54HC4040FK
Tube of 150
Tube of 55
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
ꢒ ꢘ ꢣ ꢛ ꢚꢦ ꢡꢠ ꢞꢟ ꢠꢚ ꢜꢣ ꢥꢗ ꢝꢘ ꢞ ꢞꢚ ꢭꢍ ꢮꢋ ꢕꢑ ꢯ ꢋꢰꢱꢂ ꢰꢂꢇ ꢝꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢝ ꢛ ꢢ ꢞꢢ ꢟꢞꢢ ꢦ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢃꢆ ꢃꢆ ꢇ ꢀ ꢁꢈ ꢃ ꢄꢅꢃ ꢆ ꢃ ꢆ
ꢉꢊ ꢋꢌꢍ ꢎ ꢏ ꢀꢐꢁ ꢅ ꢄꢑ ꢒꢁ ꢒꢓꢀ ꢌꢍ ꢁ ꢏꢑꢐ ꢅꢒ ꢓꢁꢎ ꢔꢑ ꢀ
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003
FUNCTION TABLE
(each buffer)
INPUTS
FUNCTION
CLK
CLR
L
↑
↓
X
No change
Advance to next stage
All outputs L
L
H
logic diagram (positive logic)
11
CLR
R
R
T
R
R
R
10
CLK
T
T
T
T
9
7
6
5
3
Q
Q
Q
Q
Q
E
A
B
C
D
R
T
R
R
R
R
R
R
T
T
T
T
T
T
2
4
13
12
14
15
1
Q
Q
Q
Q
Q
Q
Q
L
F
G
H
I
J
K
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢃ ꢆꢃ ꢆ ꢇ ꢀꢁꢈ ꢃꢄ ꢅꢃ ꢆꢃ ꢆ
ꢉ ꢊ ꢋꢌꢍ ꢎ ꢏꢀ ꢐꢁꢅꢄꢑ ꢒꢁ ꢒꢓ ꢀ ꢌꢍ ꢁꢏꢑꢐ ꢅꢒ ꢓ ꢁꢎ ꢔꢑ ꢀ
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
SN54HC4040
MIN NOM MAX
SN74HC4040
MIN NOM MAX
UNIT
V
V
Supply voltage
2
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
0
0
V
V
V
I
CC
CC
Output voltage
V
CC
V
CC
O
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
†
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
−55
−40
°C
†
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
IL
IH
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
= 2 V does not damage the device; however, functionally,
t
CC
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC4040 SN74HC4040
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
V
V
V = V or V
IH
V
OH
OL
I
IL
I
I
= −4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= −5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
8
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
V = V or V
V
I
IH
IL
I
I
= 4 mA
4.5 V
6 V
0.4
0.33
0.33
1000
80
OL
= 5.2 mA
0.4
OL
I
I
V = V
I
or 0
6 V
1000
160
10
nA
µA
pF
I
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
CC
C
2 V to 6 V
3
10
10
i
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢃꢆ ꢃꢆ ꢇ ꢀ ꢁꢈ ꢃ ꢄꢅꢃ ꢆ ꢃ ꢆ
ꢉꢊ ꢋꢌꢍ ꢎ ꢏ ꢀꢐꢁ ꢅ ꢄꢑ ꢒꢁ ꢒꢓꢀ ꢌꢍ ꢁ ꢏꢑꢐ ꢅꢒ ꢓꢁꢎ ꢔꢑ ꢀ
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC4040 SN74HC4040
A
V
UNIT
CC
MIN
MAX
5.5
28
MIN
MAX
3.7
19
MIN
MAX
4.3
22
2 V
4.5 V
6 V
f
t
t
Clock frequency
MHz
clock
33
22
25
2 V
90
18
15
70
14
12
60
12
10
135
27
115
23
20
90
18
15
75
15
13
4.5 V
6 V
CLK high or low
CLR high
23
Pulse duration
ns
ns
w
2 V
105
21
4.5 V
6 V
18
2 V
90
Setup time, CLR inactive before CLK↓
4.5 V
6 V
18
su
15
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
10
SN54HC4040 SN74HC4040
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
5.5
28
MAX
MIN
3.7
19
MAX
MIN
4.3
22
MAX
2 V
4.5 V
6 V
45
f
t
t
t
MHz
max
33
53
22
25
2 V
62
150
30
225
45
190
38
4.5 V
6 V
16
CLK
CLR
Q
ns
ns
ns
pd
A
12
26
38
32
2 V
63
140
28
210
42
175
35
4.5 V
6 V
17
Any
Any
PHL
t
13
24
36
30
2 V
28
75
110
22
95
4.5 V
6 V
8
15
19
6
13
19
16
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
88
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢉ ꢊ ꢋꢌꢍ ꢎ ꢏꢀ ꢐꢁꢅꢄꢑ ꢒꢁ ꢒꢓ ꢀ ꢌꢍ ꢁꢏꢑꢐ ꢅꢒ ꢓ ꢁꢎ ꢔꢑ ꢀ
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
50%
50%
50%
Pulse
From Output
Under Test
Test
Point
0 V
t
w
C
= 50 pF
L
V
CC
(see Note A)
Low-Level
Pulse
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
85004012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
85004012A
SNJ54HC
4040FK
8500401EA
8500401FA
ACTIVE
ACTIVE
CDIP
CFP
J
16
16
1
1
TBD
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
8500401EA
SNJ54HC4040J
W
8500401FA
SNJ54HC4040W
SN54HC4040J
SN74HC4040D
ACTIVE
ACTIVE
CDIP
SOIC
J
16
16
1
A42
N / A for Pkg Type
-55 to 125
-40 to 85
SN54HC4040J
D
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HC4040
SN74HC4040DBLE
SN74HC4040DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
16
16
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HC4040
HC4040
HC4040
HC4040
HC4040
HC4040
HC4040
HC4040
HC4040
HC4040
HC4040
SN74HC4040DBRE4
SN74HC4040DBRG4
SN74HC4040DE4
SN74HC4040DG4
SN74HC4040DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DB
DB
D
16
16
16
16
16
16
16
16
16
16
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
D
40
Green (RoHS
& no Sb/Br)
D
2500
2500
2500
250
Green (RoHS
& no Sb/Br)
SN74HC4040DRE4
SN74HC4040DRG4
SN74HC4040DT
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
SN74HC4040DTE4
SN74HC4040DTG4
D
250
Green (RoHS
& no Sb/Br)
D
250
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74HC4040DWR
SN74HC4040N
OBSOLETE
ACTIVE
SOIC
PDIP
DW
16
16
TBD
Call TI
Call TI
-40 to 85
-40 to 85
N
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74HC4040N
SN74HC4040N3
SN74HC4040NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
16
16
TBD
Call TI
Call TI
-40 to 85
-40 to 85
25
2000
2000
2000
90
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74HC4040N
HC4040
SN74HC4040NSR
SN74HC4040NSRE4
SN74HC4040NSRG4
SN74HC4040PW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
SO
NS
NS
NS
PW
PW
PW
16
16
16
16
16
16
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
HC4040
SO
Green (RoHS
& no Sb/Br)
HC4040
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
HC4040
SN74HC4040PWE4
SN74HC4040PWG4
90
Green (RoHS
& no Sb/Br)
HC4040
90
Green (RoHS
& no Sb/Br)
HC4040
SN74HC4040PWLE
SN74HC4040PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
250
250
250
1
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HC4040
HC4040
HC4040
HC4040
HC4040
HC4040
SN74HC4040PWRE4
SN74HC4040PWRG4
SN74HC4040PWT
SN74HC4040PWTE4
SN74HC4040PWTG4
SNJ54HC4040FK
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
LCCC
PW
PW
PW
PW
PW
FK
16
16
16
16
16
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TBD
85004012A
SNJ54HC
4040FK
SNJ54HC4040J
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8500401EA
SNJ54HC4040J
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
SNJ54HC4040W
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
8500401FA
SNJ54HC4040W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC4040, SN74HC4040 :
Catalog: SN74HC4040
•
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Military: SN54HC4040
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
•
Military - QML certified for Military and Defense Applications
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC4040DBR
SN74HC4040DR
SN74HC4040DR
SN74HC4040PWR
SN74HC4040PWT
SSOP
SOIC
DB
D
16
16
16
16
16
2000
2500
2500
2000
250
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
12.4
12.4
8.2
6.5
6.5
6.9
6.9
6.6
10.3
10.3
5.6
2.5
2.1
2.1
1.6
1.6
12.0
8.0
8.0
8.0
8.0
16.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
SOIC
D
TSSOP
TSSOP
PW
PW
5.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HC4040DBR
SN74HC4040DR
SN74HC4040DR
SN74HC4040PWR
SN74HC4040PWT
SSOP
SOIC
DB
D
16
16
16
16
16
2000
2500
2500
2000
250
367.0
367.0
333.2
367.0
367.0
367.0
367.0
345.9
367.0
367.0
38.0
38.0
28.6
35.0
35.0
SOIC
D
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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