SN74HC573A [TI]
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS; 八路透明D类锁存器具有三态输出
| 型号： | SN74HC573A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总16页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢂ ꢆꢇ ꢈ ꢉ ꢀꢁꢆ ꢃꢄ ꢅꢂ ꢆꢇ ꢈ
ꢊ ꢅꢋꢈꢌ ꢋ ꢍꢈꢁꢀ ꢎꢈꢍꢏ ꢁꢋ ꢐꢑꢋ ꢒꢎ ꢏ ꢌꢈꢋꢅ ꢄ ꢏꢀ
ꢓ ꢔꢋ ꢄ ꢇ ꢑꢀꢋꢈꢋ ꢏ ꢊ ꢕꢋ ꢎꢕ ꢋꢀ
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
D
Typical t = 21 ns
pd
High-Current 3-State Outputs Drive Bus
Lines Directly or Up To 15 LSTTL Loads
D
D
D
6-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Bus-Structured Pinout
Low Power Consumption, 80-µA Max I
CC
SN54HC573A . . . J OR W PACKAGE
SN74HC573A . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
SN54HC573A . . . FK PACKAGE
(TOP VIEW)
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1Q
2Q
1
2
3
4
5
6
7
8
9
20
19
18
3
2
1
20 19
18
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
4
5
6
7
8
17
16
15
14
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 LE
9 10 11 12 13
GND 10
description/ordering information
These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive
or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the
outputs are latched to retain the data that was set up.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 25
Tube of 40
Reel of 2500
Reel of 2000
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HC573AN
SN74HC573AN
SN74HC573ADW
SN74HC573ADWR
SN74HC573ADBR
SN74HC573APWR
SN74HC573APWT
SNJ54HC573AJ
SOIC − DW
SSOP − DB
HC573A
HC573A
−40°C to 85°C
TSSOP − PW
HC573A
CDIP − J
CFP − W
LCCC − FK
SNJ54HC573AJ
SNJ54HC573AW
SNJ54HC573AFK
−55°C to 125°C
SNJ54HC573AW
SNJ54HC573AFK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢇꢈ ꢉ ꢀ ꢁꢆ ꢃ ꢄꢅꢂ ꢆ ꢇ ꢈ
ꢊꢅ ꢋꢈ ꢌ ꢋ ꢍ ꢈꢁ ꢀꢎꢈꢍ ꢏꢁ ꢋ ꢐꢑꢋ ꢒ ꢎꢏ ꢌꢈꢋꢅ ꢄꢏꢀ
ꢓꢔ ꢋ ꢄ ꢇ ꢑꢀꢋꢈꢋ ꢏ ꢊꢕꢋ ꢎ ꢕꢋꢀ
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
11
LE
C1
1D
19
1Q
2
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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ꢊ ꢅꢋꢈꢌ ꢋ ꢍꢈꢁꢀ ꢎꢈꢍꢏ ꢁꢋ ꢐꢑꢋ ꢒꢎ ꢏ ꢌꢈꢋꢅ ꢄ ꢏꢀ
ꢓ ꢔꢋ ꢄ ꢇ ꢑꢀꢋꢈꢋ ꢏ ꢊ ꢕꢋ ꢎ ꢕꢋꢀ
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
SN54HC573A
MIN NOM MAX
SN74HC573A
MIN NOM MAX
UNIT
V
V
Supply voltage
2
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
0
0
V
V
V
I
CC
CC
Output voltage
V
CC
V
CC
O
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
= 4.5 V
= 6 V
t
t
Input transition (rise and fall) time
Operating free-air temperature
ns
T
A
−55
−40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC573A SN74HC573A
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
V
V = V or V
IH
V
OH
OL
I
IL
IL
I
I
= −6 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= −7.8 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
0.5
8
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
V
V = V or V
V
I
IH
I
I
= 6 mA
4.5 V
6 V
0.4
0.33
0.33
1000
5
OL
= 7.8 mA
0.4
OL
I
I
I
V = V
I
or 0
6 V
1000
10
nA
µA
µA
pF
I
CC
V
O
= V
or 0
6 V
0.01
OZ
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
160
10
80
CC
C
2 V to 6 V
3
10
10
i
3
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ꢊꢅ ꢋꢈ ꢌ ꢋ ꢍ ꢈꢁ ꢀꢎꢈꢍ ꢏꢁ ꢋ ꢐꢑꢋ ꢒ ꢎꢏ ꢌꢈꢋꢅ ꢄꢏꢀ
ꢓꢔ ꢋ ꢄ ꢇ ꢑꢀꢋꢈꢋ ꢏ ꢊꢕꢋ ꢎ ꢕꢋꢀ
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC573A SN74HC573A
A
V
UNIT
CC
MIN
80
16
14
50
10
9
MAX
MIN
120
24
20
75
15
13
24
5
MAX
MIN
100
20
17
63
13
11
24
5
MAX
2 V
4.5 V
6 V
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
2 V
4.5 V
6 V
ns
ns
2 V
20
5
4.5 V
6 V
5
5
5
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
77
26
23
87
27
23
68
24
21
47
23
21
28
8
SN54HC573A SN74HC573A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
175
35
MIN
MAX
265
53
MIN
MAX
220
44
2 V
4.5 V
6 V
D
Q
30
45
38
t
pd
ns
2 V
175
35
265
53
220
44
4.5 V
6 V
LE
OE
OE
Any Q
Any Q
Any Q
Any Q
30
45
38
2 V
150
30
225
45
190
38
4.5 V
6 V
t
t
t
ns
ns
ns
en
dis
t
26
38
32
2 V
150
30
225
45
190
38
4.5 V
6 V
26
38
32
2 V
60
90
75
4.5 V
6 V
12
18
15
6
10
15
13
4
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ꢓ ꢔꢋ ꢄ ꢇ ꢑꢀꢋꢈꢋ ꢏ ꢊ ꢕꢋ ꢎ ꢕꢋꢀ
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
95
SN54HC573A SN74HC573A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
200
40
MIN
MAX
300
60
MIN
MAX
250
50
2 V
4.5 V
6 V
33
D
Q
21
34
51
43
t
pd
ns
2 V
103
33
225
45
335
67
285
57
4.5 V
6 V
LE
OE
Any Q
Any Q
Any Q
29
38
57
48
2 V
85
200
40
300
60
250
50
4.5 V
6 V
29
t
t
ns
ns
en
26
34
51
43
2 V
60
210
42
315
63
265
53
4.5 V
6 V
17
t
14
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance per latch
No load
50
pF
pd
5
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ꢓꢔ ꢋ ꢄ ꢇ ꢑꢀꢋꢈꢋ ꢏ ꢊꢕꢋ ꢎ ꢕꢋꢀ
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
S1
S2
L
L
50 pF
or
150 pF
S1
S2
t
t
t
t
Open
Closed
PZH
PZL
PHZ
PLZ
Test
Point
t
1 kΩ
en
R
L
Closed
Open
Open
Closed
Open
From Output
Under Test
t
t
1 kΩ
50 pF
C
dis
pd
L
Closed
(see Note A)
50 pF
or
150 pF
or t
−−
Open
Open
t
LOAD CIRCUIT
V
CC
Reference
Input
50%
V
CC
0 V
High-Level
Pulse
50%
50%
50%
t
t
h
su
0 V
V
CC
t
Data
Input
w
90%
90%
50%
10%
50%
10%
V
CC
0 V
Low-Level
Pulse
50%
t
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Output
Input
V
CC
50%
50%
Control
(Low-Level
Enabling)
50%
50%
0 V
V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
OH
In-Phase
Output
90%
≈V
CC
Output
Waveform 1
(See Note B)
≈V
CC
50%
50%
10%
50%
10%
V
OL
10%
t
t
f
r
V
OL
OH
t
t
PLH
PHL
90%
t
t
PZH
PHZ
V
V
OH
90%
Out-of-
Phase
Output
V
50%
10%
50%
10%
Output
Waveform 2
(See Note B)
90%
50%
OL
t
t
≈0 V
f
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CFP
Drawing
5962-8512801VRA
5962-8512801VSA
85128012A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
W
FK
J
20
20
20
20
20
20
20
20
1
None
None
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
1
LCCC
CDIP
CFP
1
8512801RA
1
1
8512801SA
W
J
JM38510/65406BRA
SN54HC573AJ
SN74HC573ADBR
CDIP
CDIP
SSOP
1
J
1
DB
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC573ADW
SN74HC573ADWR
SN74HC573AN
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
PDIP
DW
DW
N
20
20
20
25
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
ACTIVE
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74HC573AN3
SN74HC573APWLE
SN74HC573APWR
OBSOLETE
N
20
20
20
None
None
Call TI
Call TI
Call TI
Call TI
OBSOLETE TSSOP
PW
PW
ACTIVE
TSSOP
2000
250
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74HC573APWT
ACTIVE
TSSOP
PW
20
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SNJ54HC573AFK
SNJ54HC573AJ
SNJ54HC573AW
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
None
None
None
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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