SN74HC594DBLE [TI]
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| 型号： | SN74HC594DBLE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 暂无描述 移位寄存器 输出元件 |
| 文件： | 总9页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
SN54HC594 . . . J OR W PACKAGE
SN74HC594 . . . D, DB, OR N PACKAGE
(TOP VIEW)
8-Bit Serial-In, Parallel-Out Shift Registers
With Storage
Independent Direct Overriding Clears on
Shift and Storage Registers
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
Independent Clocks for Both Shift and
Storage Registers
Q
C
D
A
Q
SER
Q
RCLR
RCLK
SRCLK
SRCLR
High-Current Outputs Can Drive Up to
15 LSTTL Loads
E
Q
Q
F
Package Options Include Plastic
G
Q
Small-Outline (D), Shrink Small-Outline
(DB), and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and Standard
Plastic (N) and Ceramic (J) 300-mil DIPs
H
GND
Q
H′
SN54HC594 . . . FK PACKAGE
(TOP VIEW)
description
The ’HC594 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Separate clocks and direct
overriding clear (RCLR, SRCLR) inputs are
provided on both the shift and storage registers.
3
2
1
20 19
18
SER
RCLR
NC
Q
4
5
6
7
8
D
Q
17
16
E
NC
A serial (Q ) output is provided for cascading
15 RCLK
14
9 10 11 12 13
Q
F
H′
purposes.
SRCLK
Q
G
Boththeshiftregister(RCLK)andstorageregister
(SRCLK) clocks are positive edge triggered. If
both clocks are connected together, the shift
register is always one count pulse ahead of the
storage register.
NC – No internal connection
The parallel (Q –Q ) outputs have high-current
A
H
capability. Q is a standard output.
H′
The SN54HC594 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC594 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
†
logic symbol
13
R3
C2
RCLR
RCLK
12
SRG8
10
11
R
SRCLR
SRCLK
C1/
15
1
14
Q
Q
3
2D
SER
1D
A
B
2
Q
Q
C
D
3
4
5
6
7
9
Q
Q
E
F
Q
Q
G
H
2D
3
Q
H′
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
logic diagram (positive logic)
13
RCLR
12
RCLK
10
SRCLR
11
SRCLK
R
3R
C3
14
SER
1D
C1
15
Q
Q
A
B
R
3S
2S
2R
R
3R
1
C2
C3
R
3S
2S
2R
C2
R
3R
2
Q
Q
C
D
C3
R
3S
2S
2R
C2
R
3R
3
C3
R
3S
2S
2R
C2
R
3R
4
Q
Q
Q
E
F
C3
R
3S
2S
2R
C2
R
3R
5
C3
R
3S
2S
2R
C2
R
3R
6
G
C3
R
3S
2S
2R
C2
R
3R
C3
3S
7
9
Q
Q
H
R
H′
Pin numbers shown are for the D, DB, J, N, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
†
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions (see Note 3)
SN54HC594
MIN NOM
SN74HC594
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
3.15
4.2
0
5
6
2
1.5
3.15
4.2
0
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
High-level input voltage
= 4.5 V
= 6 V
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
0
0
0
0
V
V
Input voltage
0
V
V
0
V
V
V
V
I
CC
CC
Output voltage
0
0
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
0
1000
500
400
125
0
1000
500
400
85
t
Input transition (rise and fall) time
Operating free-air temperature
= 4.5 V
= 6 V
0
0
ns
t
0
0
T
–55
–40
°C
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC594
SN74HC594
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
3.7
5.2
5.2
MAX
MIN
1.9
MAX
2 V
1.9 1.998
4.4 4.499
5.9 5.999
I
= –20 µA
4.5 V
6 V
4.4
OH
5.9
V
OH
V = V or V
IH
Q
, I
H′ OH
= –4 mA
3.98
4.3
4.3
3.84
3.84
5.34
5.34
V
I
IL
4.5 V
6 V
Q –Q , I
= –6 mA
3.98
5.48
5.48
A
H
OH
Q
, I
H′ OH
= –5.2 mA
5.8
Q –Q , I
= –7.8 mA
5.8
A
H
OH
2 V
4.5 V
6 V
0.002
0.001
0.001
0.17
0.17
0.15
0.15
±0.1
±0.01
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
OL
0.1
0.1
0.1
V
OL
V = V or V
Q
, I
H′ OL
= 4 mA
0.26
0.26
0.26
0.26
±100
±0.5
8
0.4
0.33
0.33
0.33
0.33
±1000
±5
V
I
IH
IL
4.5 V
6 V
Q –Q , I
= 6 mA
0.4
A
H
OL
Q
, I
H′ OL
= 5.2 mA
0.4
Q –Q , I = 7.8 mA
H OL
0.4
A
I
I
I
V = V
or 0
6 V
6 V
6 V
±1000
±10
160
nA
µA
µA
I
I
CC
CC
V
O
= V
or 0
OZ
CC
CC
V = V
I
or 0,
I
O
= 0
80
2 V
to 6 V
C
3
10
10
10
pF
i
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC594
SN74HC594
A
V
UNIT
CC
MIN
MAX
5
MIN
MAX
3.3
17
MIN
MAX
4
2 V
f
Clock frequency
Pulse duration
4.5 V
6 V
25
20
MHz
clock
29
20
24
2 V
100
20
17
100
20
17
90
18
15
90
18
15
50
10
9
150
30
25
150
30
25
135
27
23
135
27
23
75
15
13
20
10
10
5
125
25
21
125
25
21
110
22
19
110
22
19
63
13
11
20
10
10
5
SRCLK or RCLK high or low
SRCLR or RCLR low
4.5 V
6 V
t
w
ns
2 V
4.5 V
6 V
2 V
SER before SRCLK↑
4.5 V
6 V
2 V
†
SRCLK↑ before RCLK↑
4.5 V
6 V
2 V
t
su
Setup time
SRCLR low before RCLK↑
4.5 V
6 V
ns
2 V
20
10
10
5
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before SRCLK↑
4.5 V
6 V
2 V
4.5 V
6 V
5
5
5
5
5
5
2 V
5
5
5
t
h
Hold time, SER after SRCLK↑
4.5 V
6 V
5
5
5
ns
5
5
5
†
This setup time ensures the output register sees stable data from the shift-register outputs. The clocks may be tied together, in which case the
output register is one clock pulse behind the shift register.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
8
SN54HC594
SN74HC594
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
5
MAX
MIN
3.3
17
MAX
MIN
4
MAX
2 V
f
4.5 V
6 V
25
29
35
40
50
20
15
50
20
15
50
20
15
50
20
15
38
8
20
24
MHz
max
pd
20
2 V
150
30
225
45
185
37
SRCLK
RCLK
Q
4.5 V
6 V
H′
25
38
31
t
ns
ns
ns
2 V
150
30
225
45
185
37
Q –Q
A
4.5 V
6 V
H
H
H
25
38
31
2 V
150
30
225
45
185
37
SRCLR
RCLR
Q
4.5 V
6 V
H′
25
38
31
t
PHL
2 V
125
25
185
37
155
31
Q –Q
A
4.5 V
6 V
21
31
26
2 V
75
110
22
95
Q
4.5 V
6 V
15
19
H′
6
13
19
16
t
t
2 V
38
8
60
90
75
Q –Q
A
4.5 V
6 V
12
18
15
6
10
15
13
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
90
SN54HC594
SN74HC594
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
200
40
MIN
MAX
300
60
MIN
MAX
250
50
2 V
t
t
t
RCLK
RCLR
Q –Q
A
4.5 V
6 V
23
ns
pd
PHL
t
H
H
H
19
34
51
43
2 V
90
200
40
300
60
250
50
Q –Q
A
4.5 V
6 V
23
ns
ns
19
34
51
43
2 V
45
210
42
315
63
265
53
Q –Q
A
4.5 V
6 V
17
13
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
395
pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
Pulse
50%
50%
50%
From Output
Under Test
Test
Point
0 V
t
w
C
L
V
CC
(see Note A)
Low-Level
Pulse
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
90%
50%
50%
10%
50%
10%
V
OL
0 V
V
t
f
r
t
h
t
su
t
t
PLH
PHL
V
CC
OH
OL
Data
Input
90%
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
f
t
t
f
r
r
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
PLH
PHL pd
F. t and t are the same as t .
f
r
t
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 1998, Texas Instruments Incorporated
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