SN74HCS125BQA-Q1 [TI]
SN74HCS125-Q1 Automotive Quadruple Buffer with 3-State Outputs and Schmitt-Trigger Inputs;
| 型号： | SN74HCS125BQA-Q1 |
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TEXAS INSTRUMENTS |
| 描述： | SN74HCS125-Q1 Automotive Quadruple Buffer with 3-State Outputs and Schmitt-Trigger Inputs |
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SN74HCS125-Q1
SCLS752A – APRIL 2020 – REVISED MARCH 2021
SN74HCS125-Q1 Automotive Quadruple Buffer with 3-State Outputs and Schmitt-
Trigger Inputs
1 Features
3 Description
•
AEC-Q100 Qualified for automotive applications:
– Device temperature grade 1:
–40°C to +125°C, TA
– Device HBM ESD Classification Level 2
– Device CDM ESD Classifcation Level C6
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input
signals
The SN74HCS125-Q1 contains four independent
buffers with 3-state outputs and Schmitt-trigger inputs.
Each buffer performs the Boolean function Y = A in
positive logic. The outputs can be put into a Hi-Z state
by applying a High on the OE pin.
•
•
Device Information
PART NUMBER
PACKAGE(1)
TSSOP (14)
SOIC (14)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
9.90 mm × 3.90 mm
3.00 mm × 2.50 mm
SN74HCS125PW-Q1
SN74HCS125D-Q1
SN74HCS125BQA-Q1
•
Low power consumption
– Typical ICC of 100 nA
WQFN (14)
– Typical input leakage current of ±100 nA
±7.8-mA output drive at 6 V
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
2 Applications
•
•
•
•
Enable or disable a digital signal
Controlling an indicator LED
Debounce a switch
Eliminate slow or noisy input signals
Supports Slow Inputs
Low Power
Noise Rejection
Input Voltage
Waveforms
Time
Input Voltage
Time
Standard
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
Schmitt-trigger
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
Benefits of Schmitt-trigger inputs
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HCS125-Q1
SCLS752A – APRIL 2020 – REVISED MARCH 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Switching Characteristics ...........................................5
6.7 Operating Characteristics .......................................... 6
6.8 Typical Characteristics................................................7
7 Parameter Measurement Information............................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................14
11 Layout...........................................................................14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 14
12 Device and Documentation Support..........................15
12.1 Documentation Support.......................................... 15
12.2 Receiving Notification of Documentation Updates..15
12.3 Support Resources................................................. 15
12.5 Electrostatic Discharge Caution..............................15
12.6 Glossary..................................................................15
13 Mechanical, Packaging, and Orderable
Information.................................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (April 2020) to Revision A (March 2021)
Page
•
•
•
•
Updated the numbering fomat for tables, figures and cross-references throughout the document....................1
Added BQA package information to Device Information ................................................................................... 1
Added BQA package to Pin Configuration and Functions .................................................................................3
Added BQA package information to Thermal Information table......................................................................... 5
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5 Pin Configuration and Functions
1OE VCC
1
2
14
13
VCC
1OE
1A
1
14
4OE
4A
1A
1Y
2
3
4
4OE
4A
13
12
11
10
3
4
12
11
1Y
4Y
2OE
2A
5
10
PAD
2OE
2A
3OE
3A
4Y
6
7
9
8
2Y
5
6
3OE
3A
GND
3Y
2Y
9
7
GND 3Y
8
D or PW Package
14-Pin SOIC or TSSOP
Top View
Figure 5-1. BQA Package
14-Pin WQFN
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
1 OE
1A
NO.
1
2
Input
Input
Output
Input
Input
Output
—
Channel 1, Output Enable, Active Low
Channel 1, Input A
1Y
3
Channel 1, Output Y
2 OE
2A
4
Channel 2, Output Enable, Active Low
Channel 2, Input A
5
2Y
6
Channel 2, Output Y
GND
3Y
7
Ground
8
Output
Input
Input
Output
Input
Input
—
Channel 3, Output Y
3A
9
Channel 3, Input A
3 OE
4Y
10
11
12
13
14
Channel 3, Output Enable, Active Low
Channel 4, Output Y
4A
Channel 4, Input A
4 OE
VCC
Channel 4, Output Enable, Active Low
Positive Supply
—
The thermal pad can be connected to GND or left floating. Do not connect to any other
signal or supply.
Thermal Pad(1)
1. BQA package only.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
7
UNIT
V
VCC
IIK
Supply voltage
–0.5
Input clamp current(2)
VI < 0 or VI > VCC
VO < 0 or VO > VCC
VO = 0 to VCC
±20
±20
±35
±70
150
150
mA
mA
mA
mA
°C
IOK
IO
Output clamp current(2)
Continuous output current
Continuous current through VCC or GND
Junction temperature
ICC
TJ
Tstg
Storage temperature
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±4000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC
Q100-011
±1000
CDM ESD Classification Level C4B
(1) AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2
NOM
MAX
6
UNIT
V
VCC
VI
Supply voltage
Input voltage
5
0
VCC
VCC
125
V
VO
TA
Output voltage
Ambient temperature
0
V
–55
°C
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6.4 Thermal Information
SN74HCS125-Q1
PW (TSSOP)
14 PINS
151.7
THERMAL METRIC(1)
D (SOIC)
14 PINS
133.6
89
BQA (WQFN)
14 PINS
109.7
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
79.4
111.0
RθJB
ΨJT
Junction-to-board thermal resistance
89.5
94.7
77.9
Junction-to-top characterization
parameter
45.5
89.1
N/A
25.2
94.1
N/A
20.2
77.8
56.6
°C/W
°C/W
°C/W
Junction-to-board characterization
parameter
ΨJB
Junction-to-case (bottom) thermal
resistance
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VCC
MIN
0.7
1.7
2.1
0.3
0.9
1.2
0.2
0.4
0.6
TYP(1)
MAX UNIT
2 V
1.5
VT+
Positive switching threshold
4.5 V
6 V
3.15
4.2
1
V
V
V
V
V
2 V
VT-
Negative switching threshold
Hysteresis (VT+ - VT-)(1)
4.5 V
6 V
2.2
3
2 V
1
ΔVT
VOH
VOL
4.5 V
6 V
1.4
1.6
IOH = -20 µA
VI = VIH or VIL IOH = -6 mA
IOH = -7.8 mA
2 V to 6 V
4.5 V
6 V
VCC – 0.1 VCC – 0.002
High-level output voltage
4
4.3
5.75
5.4
IOL = 20 µA
2 V to 6 V
4.5 V
6 V
0.002
0.18
0.1
0.3
Low-level output voltage
Input leakage current
VI = VIH or VIL IOL = 6 mA
IOL = 7.8 mA
0.22
0.33
II
VI = VCC or 0
6 V
±100
±1000 µA
Off-state (high-impedance
state) output current
IOZ
VO = VCC or 0
6 V
0.01
0.1
2
µA
ICC
Ci
Supply current
VI = VCC or 0, IO = 0
6 V
2
5
µA
pF
Input capacitance
2 V to 6 V
(1) TA = 25°C
6.6 Switching Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter
Measurement Information.
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
2 V
MIN
TYP
12
6
MAX UNIT
39
tpd
Propagation delay
A
Y
4.5 V
6 V
26
24
ns
5
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over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter
Measurement Information.
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
MIN
TYP
14
7
MAX UNIT
2 V
24
ten
tdis
tt
Enable time
OE
Y
Y
4.5 V
6 V
10
9
ns
ns
ns
6
2 V
12
9
16
10
9
Disable time
OE
4.5 V
6 V
8
2 V
9
16
9
Transition-time
Any
4.5 V
6 V
5
4
8
6.7 Operating Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Cpd
Power dissipation capacitance per gate
No load
10
pF
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6.8 Typical Characteristics
TA = 25°C
46
44
42
40
38
36
34
32
30
28
26
70
65
60
55
50
45
40
35
30
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Sink Current (mA)
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Source Current (mA)
Figure 6-1. Output driver resistance in LOW state. Figure 6-2. Output driver resistance in HIGH state.
0.2
0.18
0.16
0.14
0.12
0.1
0.65
0.6
VCC = 2 V
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0.55
0.5
VCC = 2.5 V
VCC = 3.3 V
0.45
0.4
0.35
0.3
0.08
0.06
0.04
0.02
0
0.25
0.2
0.15
0.1
0.05
0
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VI œ Input Voltage (V)
VI œ Input Voltage (V)
Figure 6-3. Supply current across input voltage, 2-,
2.5-, and 3.3-V supply
Figure 6-4. Supply current across input voltage,
4.5-, 5-, and 6-V supply
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
VCC
VCC
0 V
VOH
VOL
VOH
VOL
Test
Point
Input
Output
Output
50%
50%
S1
S2
RL
(1)
(1)
From Output
Under Test
tPLH
tPHL
(1)
CL
50%
50%
(1)
(1)
(1) CL includes probe and test-fixture capacitance.
tPHL
tPLH
Figure 7-1. Load Circuit for 3-State Outputs
50%
50%
(1) The greater between tPLH and tPHL is the same as tpd
.
Figure 7-2. Voltage Waveforms Propagation Delays
VCC
VCC
90%
10%
90%
Output
Control
50%
50%
Input
10%
tf(1)
0 V
0 V
VOH
VOL
tr(1)
(3)
(4)
tPZL
tPLZ
≈ VCC
90%
10%
90%
Output
Waveform 1
(1)
S1 at VLOAD
50%
Output
10%
10%
tf(1)
VOL
tr(1)
(3)
(4)
tPZH
tPHZ
(1) The greater between tr and tf is the same as tt.
VOH
Output
Waveform 2
S1 at GND(2)
90%
Figure 7-4. Voltage Waveforms, Input and Output
Transition Times
50%
≈ 0 V
Figure 7-3. Voltage Waveforms Propagation Delays
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8 Detailed Description
8.1 Overview
This device contains four independent buffers with 3-state outputs and Schmitt-trigger inputs. Each buffer
performs the Boolean function Y = A in positive logic. The outputs can be put into a Hi-Z state by applying a High
on the OE pin.
8.2 Functional Block Diagram
One of Four Channels
xOE
xA
xY
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.2 CMOS Schmitt-Trigger Inputs
This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are
typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table
from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the
Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics
table, using Ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics
table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional
information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
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VCC
Logic
GND
Device
+IIK
+IOK
Input
Output
-IIK
-IOK
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Function Table lists the functional modes of the SN74HCS125-Q1.
Table 8-1. Function Table
INPUTS(1)
OUTPUT
OE
A
H
L
Y
H
L
L
L
H
X
Z
(1) H = High Voltage Level, L =
Low Voltage Level, X = Don't
Care
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, a buffer with a 3-state output is used to disable a data signal as shown in Figure 9-1. The
remaining three buffers can be used for signal conditioning in other places in the system, or the inputs can be
grounded and the channels left unused.
9.2 Typical Application
System
Controller
OE
A
Y
Data
Output
Figure 9-1. Typical application block diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74HCS125-Q1 plus the maximum static supply current, ICC, listed in Electrical Characteristics
and any transient current required for switching. The logic device can only source as much current as is provided
by the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the
Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HCS125-Q1 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current as can be sunk into its ground
connection. Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74HCS125-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting
all of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to
exceed 50 pF.
The SN74HCS125-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state,
the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
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CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS125-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS125-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure
optimal performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HCS125-Q1 to the receiving device(s).
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
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9.2.3 Application Curves
OE
Data
Output
Figure 9-2. Application timing diagram
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to
the device
0.1 ꢀF
Unused inputs
tied to VCC
1OE
1A
14
1
2
3
4
5
6
7
VCC
13
12
11
10
9
4OE
4A
1Y
Unused output
left floating
2OE
2A
4Y
3OE
3A
2Y
Avoid 90°
corners for
signal lines
GND
8
3Y
Figure 11-1. Example layout for the SN74HCS125-Q1
Copyright © 2021 Texas Instruments Incorporated
14
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Product Folder Links: SN74HCS125-Q1
SN74HCS125-Q1
SCLS752A – APRIL 2020 – REVISED MARCH 2021
www.ti.com
12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, HCMOS Design Considerations application report (SCLA007)
Texas Instruments, CMOS Power Consumption and Cpd Calculation application report (SDYA009)
Texas Instruments, Designing With Logic application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
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Product Folder Links: SN74HCS125-Q1
SN74HCS125-Q1
SCLS752A – APRIL 2020 – REVISED MARCH 2021
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: SN74HCS125-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74HCS125QBQARQ1
SN74HCS125QDRQ1
SN74HCS125QPWRQ1
ACTIVE
ACTIVE
ACTIVE
WQFN
SOIC
BQA
D
14
14
14
3000 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
HS125Q
NIPDAU
NIPDAU
HCS125Q1
HCS125Q
TSSOP
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Mar-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74HCS125-Q1 :
Catalog : SN74HCS125
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCS125QBQARQ1 WQFN
SN74HCS125QDRQ1 SOIC
SN74HCS125QPWRQ1 TSSOP
BQA
D
14
14
14
3000
2500
2000
180.0
330.0
330.0
12.4
16.4
12.4
2.8
6.5
6.9
3.3
9.0
5.6
1.1
2.1
1.6
4.0
8.0
8.0
12.0
16.0
12.0
Q1
Q1
Q1
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HCS125QBQARQ1
SN74HCS125QDRQ1
SN74HCS125QPWRQ1
WQFN
SOIC
BQA
D
14
14
14
3000
2500
2000
210.0
853.0
853.0
185.0
449.0
449.0
35.0
35.0
35.0
TSSOP
PW
Pack Materials-Page 2
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD
BQA0014A
A
2.6
2.4
B
3.1
2.9
PIN 1 INDEX AREA
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
1.1
0.9
(0.2) TYP
2X 0.5
7
8
8X 0.5
6
9
SYMM
2X
2
1.6
1.4
15
13
2
0.3
14X
0.2
0.1
1
14
PIN 1 ID
(OPTIONAL)
C A B
C
0.5
0.3
SYMM
14X
0.05
4224636/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
BQA0014A
PLASTIC QUAD FLAT PACK-NO LEAD
(2.3)
(1)
2X (0.5)
14
1
2
13
8X (0.5)
2X (0.5)
SYMM
(2)
(1.5) (2.8)
9
6
14X (0.25)
14X (0.6)
(Ø0.2) VIA
TYP
7
8
SYMM
(R0.05) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
0.07 MIN
ALL AROUND
METAL
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
NON-SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
4224636/A 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
BQA0014A
PLASTIC QUAD FLAT PACK-NO LEAD
(2.3)
(0.95)
2X (0.5)
14
1
2
13
8X (0.5)
SYMM
(2)
(1.38) (2.8)
9
6
14X (0.25)
14X (0.6)
7
8
SYMM
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
88% PRINTED COVERAGE BY AREA
SCALE: 20X
4224636/A 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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