SN74HCS126PWR [TI]

具有三态输出的施密特触发输入四路总线缓冲门 | PW | 14 | -40 to 125;


型号：	SN74HCS126PWR
厂家：	TEXAS INSTRUMENTS
描述：	具有三态输出的施密特触发输入四路总线缓冲门 \| PW \| 14 \| -40 to 125
文件：	总24页 (文件大小：1176K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74HCS126

ZHCSNK7B –JUNE 2020 –REVISED MAY 2023

具有三态输出和施密特触发器输入的SN74HCS126 四路缓冲器

1 特性

2 应用

• 宽工作电压范围：2V 至6V

• 施密特触发输入可实现慢速或高噪声输入信号

• 低功耗

• 启用或禁用数字信号

• 控制指示灯LED

• 对开关进行去抖

• 消除缓慢或嘈杂输入信号

– I_CC典型值为100nA

– 输入泄漏电流典型值为±100nA

• 电压为6V 时，输出驱动为±7.8mA

• 工作环境温度范围：–40°C 至+125°C，T_A

3 说明

该器件包含四个具有三态输出和施密特触发输入的独立

缓冲器。每个逻辑门以正逻辑执行布尔函数 Y = A。通

过对OE 引脚施加低电平，可以将输出置于高阻态

封装信息

封装⁽¹⁾

TSSOP (14)

SOIC (14)

封装尺寸（标称值）

5.00mm × 4.40mm

9.90mm × 3.90mm

器件型号

SN74HCS126PW

SN74HCS126D

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

Supports Slow Inputs

Low Power

Noise Rejection

Input Voltage

Waveforms

Time

Input Voltage

Time

Standard

CMOS Input

Response

Waveforms

Time

Input Voltage

Schmitt-trigger

CMOS Input

Response

Waveforms

Time

Input Voltage

施密特触发输入的优势

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCLS798

SN74HCS126

ZHCSNK7B –JUNE 2020 –REVISED MAY 2023

www.ti.com.cn

Table of Contents

8.3 Feature Description.....................................................8

8.4 Device Functional Modes............................................9

9 Application and Implementation..................................10

9.1 Application Information............................................. 10

9.2 Typical Application.................................................... 10

10 Power Supply Recommendations..............................13

11 Layout...........................................................................13

11.1 Layout Guidelines................................................... 13

11.2 Layout Example...................................................... 13

12 Device and Documentation Support..........................14

12.1 Documentation Support.......................................... 14

12.2 接收文档更新通知................................................... 14

12.3 支持资源..................................................................14

12.4 Trademarks.............................................................14

12.5 静电放电警告.......................................................... 14

12.6 术语表..................................................................... 14

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings ....................................... 4

6.2 ESD Ratings .............................................................. 4

6.3 Recommended Operating Conditions ........................4

6.4 Thermal Information ...................................................4

6.5 Electrical Characteristics ............................................5

6.6 Switching Characteristics ...........................................5

6.7 Operating Characteristics .......................................... 6

6.8 Typical Characteristics................................................6

7 Parameter Measurement Information............................7

8 Detailed Description........................................................8

8.1 Overview.....................................................................8

8.2 Functional Block Diagram...........................................8

Information.................................................................... 15

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (March 2021) to Revision B (May 2023)

Page

• 将封装信息表中的引脚计数从16 更新为 14......................................................................................................1

Changes from Revision * (June 2020) to Revision A (March 2021)

Page

• Changed the unit of I_Ifrom µA to nA...................................................................................................................5

English Data Sheet: SCLS798

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5 Pin Configuration and Functions

1OE

V_CC

4OE

2OE

3OE

GND

图5-1. PW or D Package 14-Pin TSSOP or SOIC Top View

Pin Functions

I/O

DESCRIPTION

NAME

1OE

NO.

Input

Channel 1, Output Enable, Active High

Channel 1, Input A

Output

Input

Channel 1, Output Y

2OE

Channel 2, Output Enable, Active High

Channel 2, Input A

Input

Output

Channel 2, Output Y

GND

Ground

—

Output

Input

Output

Input

Channel 3, Output Y

Channel 3, Input A

3OE

Channel 3, Output Enable, Active High

Channel 4, Output Y

Channel 4, Input A

4OE

V_CC

Channel 4, Output Enable, Active High

Positive Supply

—

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V_CC

I_IK

Supply voltage

±20

±35

±70

150

–0.5

Input clamp current⁽²⁾

V_I< 0 or V_I> V_CC

V_O< 0 or V_O> V_CC

V_O= 0 to V_CC

°C

I_OK

I_O

Output clamp current⁽²⁾

Continuous output current

Continuous current through V_CCor GND

Junction temperature

I_CC

T_J

T_stg

Storage temperature

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

HBM ESD Classification Level 2

±4000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per AEC

Q100-011

±1500

CDM ESD Classification Level C4B

(1) AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_CC

V_I

Supply voltage

Input voltage

V_CC

125

V_O

T_A

Output voltage

Ambient temperature

°C

–40

6.4 Thermal Information

SN74HCS126

THERMAL METRIC⁽¹⁾

D (SOIC)

14 PINS

133.6

PW (TSSOP)

14 PINS

151.7

79.4

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

89.5

94.7

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

45.5

25.2

Ψ_JT

89.1

94.1

Ψ_JB

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

English Data Sheet: SCLS798

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

0.7

1.7

2.1

0.3

0.9

1.2

0.2

0.4

0.6

TYP⁽¹⁾

MAX UNIT

2 V

1.5

V_T+

Positive switching threshold

4.5 V

6 V

3.15

4.2

2 V

V_T-

Negative switching threshold

Hysteresis (V_T+- V_T-)

4.5 V

6 V

2.2

2 V

4.5 V

6 V

1.4

1.6

ΔV_T

V_OH

V_OL

I_OH= -20 µA

2 V to 6 V

4.5 V

6 V

V_CC–0.1 V_CC–0.002

High-level output voltage

V_I= V_IHor V_IL

I_OH= -6 mA

I_OH= -7.8 mA

4.3

5.75

5.4

I_OL= 20 µA

2 V to 6 V

4.5 V

6 V

0.002

0.18

0.1

0.3

Low-level output voltage

Input leakage current

V_I= V_IHor V_ILI_OL= 6 mA

I_OL= 7.8 mA

0.22

0.33

I_I

V_I= V_CCor 0

6 V

±100

±1000 nA

Off-state (high-impedance

state) output current

I_OZ

V_O= V_CCor 0

6 V

0.01

0.1

µA

I_CC

C_i

Supply current

V_I= V_CCor 0, I_O= 0

6 V

µA

Input capacitance

2 V to 6 V

(1) T_A= 25°C

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

FROM (INPUT)

TO (OUTPUT)

V_CC

2 V

MIN

TYP⁽¹⁾

MAX UNIT

t_pd

t_en

t_dis

t_t

Propagation delay

4.5 V

6 V

2 V

Enable time

Disable time

Transition-time

4.5 V

6 V

2 V

4.5 V

6 V

2 V

Any

4.5 V

6 V

(1) T_A= 25°C

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6.7 Operating Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

C_pd

Power dissipation capacitance per gate

No load

(1) T_A= 25°C

6.8 Typical Characteristics

T_A= 25°C

V_CC= 2 V

V_CC= 3.3 V

V_CC= 4.5 V

V_CC= 6 V

V_CC= 3.3 V

V_CC= 4.5 V

V_CC= 6 V

2.5

7.5 10 12.5 15 17.5 20 22.5 25

Output Sink Current (mA)

2.5

7.5 10 12.5 15 17.5 20 22.5 25

Output Source Current (mA)

图6-1. Output driver resistance in LOW state.

图6-2. Output driver resistance in HIGH state.

0.2

0.65

V_CC= 2 V

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 4.5 V

0.6

0.18

0.16

0.55

V_CC= 5 V

0.5

V_CC= 6 V

0.14

0.12

0.1

0.45

0.4

0.35

0.3

0.08

0.06

0.04

0.02

0.25

0.2

0.15

0.1

0.05

0.5

1.5

2.5

3.5

0.5

1.5

2.5

3.5

4.5

5.5

V_Iœ Input Voltage (V)

图6-3. Supply current across input voltage, 2-,

图6-4. Supply current across input voltage, 4.5-,

2.5-, and 3.3-V supply

5-, and 6-V supply

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7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators

having the following characteristics: PRR ≤1 MHz, Z_O= 50 Ω, t_t< 2.5 ns.

For clock inputs, f_maxis measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

V_CC

0 V

V_OH

V_OL

V_OH

V_OL

Test

Point

Input

Output

50%

S₁

S₂

R_L

(1)

From Output

Under Test

t_PLH

t_PHL

(1)

C_L

50%

(1)

(1) C_Lincludes probe and test-fixture capacitance.

t_PHL

t_PLH

图7-1. Load Circuit for 3-State Outputs

50%

(1) The greater between t_PLHand t_PHLis the same as t_pd

图7-2. Voltage Waveforms Propagation Delays

V_CC

90%

10%

90%

Output

Control

50%

Input

10%

t_f⁽¹⁾

0 V

V_OH

V_OL

t_r⁽¹⁾

(3)

(4)

t_PZL

t_PLZ

≈ V_CC

90%

10%

90%

Output

Waveform 1

(1)

S1 at V_LOAD

50%

Output

10%

t_f⁽¹⁾

V_OL

t_r⁽¹⁾

(3)

(4)

t_PZH

t_PHZ

(1) The greater between t_rand t_fis the same as t_t.

V_OH

Output

Waveform 2

S1 at GND⁽²⁾

图7-4. Voltage Waveforms, Input and Output

90%

50%

Transition Times

≈ 0 V

图7-3. Voltage Waveforms Propagation Delays

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8 Detailed Description

8.1 Overview

This device contains four independent buffer with 3-state outputs and Schmitt-trigger inputs. Each gate performs

the Boolean function Y = A in positive logic.

8.2 Functional Block Diagram

One of Four Channels

xOE

8.3 Feature Description

8.3.1 Balanced CMOS 3-State Outputs

This device includes balanced CMOS 3-State outputs. The three states that these outputs can be in are driving

high, driving low, and high impedance. The term "balanced" indicates that the device can sink and source similar

currents. The drive capability of this device may create fast edges into light loads so routing and load conditions

should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger

currents than the device can sustain without being damaged. It is important for the output power of the device to

be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute

Maximum Ratings must be followed at all times.

When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of

minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output

voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to

the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor can

be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The

value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption

limitations. Typically, a 10 kΩresistor can be used to meet these requirements.

Unused 3-state CMOS outputs should be left disconnected.

8.3.2 CMOS Schmitt-Trigger Inputs

This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are

typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table

from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the

Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics

table, using Ohm's law (R = V ÷ I).

The Schmitt-trigger input architecture provides hysteresis as defined by ΔV_Tin the Electrical Characteristics

table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much

slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the

inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional

information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers.

8.3.3 Clamp Diode Structure

The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical

Placement of Clamping Diodes for Each Input and Output.

English Data Sheet: SCLS798

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CAUTION

Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to

the device. The input and output voltage ratings may be exceeded if the input and output clamp-

current ratings are observed.

V_CC

Device

+I_IK

+I_OK

Input

Output

Logic

GND

-I_IK

-I_OK

图8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.4 Device Functional Modes

表8-1. Function Table

INPUTS

OUTPUT

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

In this application, a buffer with a 3-state output is used to disable a data signal as shown in 图 9-1. The

remaining three buffers can be used for signal conditioning in other places in the system, or the inputs can be

grounded and the channels left unused.

9.2 Typical Application

System

Controller

Data

Output

图9-1. Typical application block diagram

9.2.1 Design Requirements

9.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The

supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.

The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all

outputs of the SN74HCS126 plus the maximum static supply current, I_CC, listed in Electrical Characteristics and

any transient current required for switching. The logic device can only source as much current as is provided by

the positive supply source. Be sure not to exceed the maximum total current through V_CClisted in the Absolute

Maximum Ratings.

The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the

SN74HCS126 plus the maximum supply current, I_CC, listed in Electrical Characteristics, and any transient

current required for switching. The logic device can only sink as much current as can be sunk into its ground

connection. Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum

Ratings.

The SN74HCS126 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of

the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed

50 pF.

The SN74HCS126 can drive a load with total resistance described by R_L≥ V_O/ I_O, with the output voltage and

current defined in the Electrical Characteristics table with V_OHand V_OL. When outputting in the high state, the

output voltage in the equation is defined as the difference between the measured output voltage and the supply

voltage at the V_CCpin.

Total power consumption can be calculated using the information provided in CMOS Power Consumption and

Cpd Calculation.

Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear

and Logic (SLL) Packages and Devices.

English Data Sheet: SCLS798

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CAUTION

The maximum junction temperature, T_J(max)listed in the Absolute Maximum Ratings, is an additional

limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum

Ratings. These limits are provided to prevent damage to the device.

9.2.1.2 Input Considerations

Input signals must cross V_t-(min)to be considered a logic LOW, and V_t+(max)to be considered a logic HIGH. Do

not exceed the maximum input voltage range found in the Absolute Maximum Ratings.

Unused inputs must be terminated to either V_CCor ground. These can be directly terminated if the input is

completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used

sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used

for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the

SN74HCS126, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ

resistor value is often used due to these factors.

The SN74HCS126 has no input signal transition rate requirements because it has Schmitt-trigger inputs.

Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude

can still cause issues. To know how much noise is too much, please refer to the ΔV_T(min)in the Electrical

Characteristics. This hysteresis value will provide the peak-to-peak limit.

Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without

causing huge increases in power consumption. The typical additional current caused by holding an input at a

value other than V_CCor ground is plotted in the Typical Characteristics.

Refer to the Feature Description section for additional information regarding the inputs for this device.

9.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will

decrease the output voltage as specified by the V_OHspecification in the Electrical Characteristics. The ground

voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output

voltage as specified by the V_OLspecification in the Electrical Characteristics.

Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected

directly together. This can cause excessive current and damage to the device.

Two channels within the same device with the same input signals can be connected in parallel for additional

output drive strength.

Unused outputs can be left floating. Do not connect outputs directly to V_CCor ground.

Refer to Feature Description section for additional information regarding the outputs for this device.

9.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from V_CCto GND. The capacitor needs to be placed physically close to the

device and electrically close to both the V_CCand GND pins. An example layout is shown in the Layout

section.

2. Ensure the capacitive load at the output is ≤50 pF. This is not a hard limit, however it will ensure optimal

performance. This can be accomplished by providing short, appropriately sized traces from the

SN74HCS126 to the receiving device(s).

3. Ensure the resistive load at the output is larger than (V_CC/ I_O(max)) Ω. This will ensure that the maximum

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in megaohms; much larger than the minimum calculated above.

4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

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9.2.3 Application Curves

Data

Output

图9-2. Application timing diagram

English Data Sheet: SCLS798

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

Recommended Operating Conditions. Each V_CCterminal should have a good bypass capacitor to prevent power

disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps

to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The

bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in

given example layout image.

11 Layout

11.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many

cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a

triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left

unconnected because the undefined voltages at the outside connections result in undefined operational states.

All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the

input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular

unused input depends on the function of the device. Generally, the inputs are tied to GND or V_CC, whichever

makes more sense for the logic function or is more convenient.

11.2 Layout Example

GND V_CC

Recommend GND flood fill for

improved signal isolation, noise

reduction, and thermal dissipation

Bypass capacitor

placed close to

the device

0.1 ꢀF

Unused inputs

tied to V_CC

1OE

V_CC

4OE

Unused output

left floating

2OE

3OE

Avoid 90°

corners for

signal lines

GND

图11-1. Example layout for the SN74HCS126-Q1

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12 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed below.

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, HCMOS Design Considerations application report (SCLA007)

• Texas Instruments, CMOS Power Consumption and C_pdCalculation application report (SDYA009)

• Texas Instruments, Designing With Logic application report

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

English Data Sheet: SCLS798

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Product Folder Links: SN74HCS126

SN74HCS126

ZHCSNK7B –JUNE 2020 –REVISED MAY 2023

www.ti.com.cn

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: SN74HCS126

English Data Sheet: SCLS798

PACKAGE OPTION ADDENDUM

www.ti.com

4-May-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SN74HCS126DR

ACTIVE

SOIC

2500 RoHS & Green

2000 RoHS & Green

NIPDAU | SN

Level-1-260C-UNLIM

-40 to 125

HCS126

Samples

SN74HCS126PWR

TSSOP

NIPDAU | SN

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

4-May-2023

OTHER QUALIFIED VERSIONS OF SN74HCS126 :

Automotive : SN74HCS126-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

4-May-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74HCS126DR

SN74HCS126PWR

SOIC

2500

2000

330.0

16.4

12.4

6.6

6.5

9.3

9.0

2.1

1.6

8.0

16.0

12.0

TSSOP

6.85

6.9

5.45

5.6

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-May-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74HCS126DR

SN74HCS126PWR

SOIC

2500

2000

366.0

356.0

366.0

356.0

364.0

356.0

364.0

356.0

50.0

35.0

50.0

35.0

TSSOP

Pack Materials-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN74HCS126PWR [TI]

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